[llvm-commits] CVS: gcc-3.4/gcc/config/s390/s390.c s390.md
John Criswell
criswell at cs.uiuc.edu
Thu Feb 5 10:08:43 PST 2004
Changes in directory gcc-3.4/gcc/config/s390:
s390.c updated: 1.2 -> 1.3
s390.md updated: 1.2 -> 1.3
---
Log message:
Commit of merge from September 24, 2003 of mainline GCC. This merge now
works reasonably on Linux/x86 and probably works on Solaris/Sparc.
---
Diffs of the changes: (+278 -289)
Index: gcc-3.4/gcc/config/s390/s390.c
diff -u gcc-3.4/gcc/config/s390/s390.c:1.2 gcc-3.4/gcc/config/s390/s390.c:1.3
--- gcc-3.4/gcc/config/s390/s390.c:1.2 Fri Jan 9 10:54:31 2004
+++ gcc-3.4/gcc/config/s390/s390.c Thu Feb 5 10:05:46 2004
@@ -1631,7 +1631,7 @@
return 1;
/* Accept immediate LARL operands. */
- if (TARGET_64BIT && larl_operand (op, VOIDmode))
+ if (TARGET_CPU_ZARCH && larl_operand (op, VOIDmode))
return 1;
/* Thread-local symbols are never legal constants. This is
@@ -1730,12 +1730,12 @@
return 1;
/* Accept lliXX operands. */
- if (TARGET_64BIT
+ if (TARGET_ZARCH
&& s390_single_hi (op, DImode, 0) >= 0)
return 1;
/* Accept larl operands. */
- if (TARGET_64BIT
+ if (TARGET_CPU_ZARCH
&& larl_operand (op, VOIDmode))
return 1;
@@ -2260,7 +2260,7 @@
|| (GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (addr)))
{
/* This is a local symbol. */
- if (TARGET_64BIT && larl_operand (addr, VOIDmode))
+ if (TARGET_CPU_ZARCH && larl_operand (addr, VOIDmode))
{
/* Access local symbols PC-relative via LARL.
This is the same as in the non-PIC case, so it is
@@ -2309,7 +2309,7 @@
emit_move_insn (reg, new);
new = reg;
}
- else if (TARGET_64BIT)
+ else if (TARGET_CPU_ZARCH)
{
/* If the GOT offset might be >= 4k, we determine the position
of the GOT entry via a PC-relative LARL (@GOTENT). */
@@ -2378,7 +2378,7 @@
/* @PLT is OK as is on 64-bit, must be converted to
GOT-relative @PLTOFF on 31-bit. */
case UNSPEC_PLT:
- if (!TARGET_64BIT)
+ if (!TARGET_CPU_ZARCH)
{
rtx temp = reg? reg : gen_reg_rtx (Pmode);
@@ -2418,7 +2418,7 @@
|| (GET_CODE (op0) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (op0)))
&& GET_CODE (op1) == CONST_INT)
{
- if (TARGET_64BIT && larl_operand (op0, VOIDmode))
+ if (TARGET_CPU_ZARCH && larl_operand (op0, VOIDmode))
{
if (INTVAL (op1) & 1)
{
@@ -2625,7 +2625,7 @@
temp = gen_reg_rtx (Pmode);
emit_move_insn (temp, new);
}
- else if (TARGET_64BIT)
+ else if (TARGET_CPU_ZARCH)
{
/* If the GOT offset might be >= 4k, we determine the position
of the GOT entry via a PC-relative LARL. */
@@ -2714,7 +2714,7 @@
switch (XINT (XEXP (addr, 0), 1))
{
case UNSPEC_INDNTPOFF:
- if (TARGET_64BIT)
+ if (TARGET_CPU_ZARCH)
new = addr;
else
abort ();
@@ -3806,12 +3806,12 @@
else
continue;
- if (get_attr_length (insn) <= (TARGET_64BIT ? 6 : 4))
+ if (get_attr_length (insn) <= (TARGET_CPU_ZARCH ? 6 : 4))
continue;
*temp_used = 1;
- if (TARGET_64BIT)
+ if (TARGET_CPU_ZARCH)
{
tmp = emit_insn_before (gen_rtx_SET (Pmode, temp_reg, *label), insn);
INSN_ADDRESSES_NEW (tmp, -1);
@@ -4212,7 +4212,7 @@
/* Pool start insn switches to proper section
and guarantees necessary alignment. */
- if (TARGET_64BIT)
+ if (TARGET_CPU_ZARCH)
insn = emit_insn_after (gen_pool_start_64 (), pool->pool_insn);
else
insn = emit_insn_after (gen_pool_start_31 (), pool->pool_insn);
@@ -4253,7 +4253,7 @@
/* Pool end insn switches back to previous section
and guarantees necessary alignment. */
- if (TARGET_64BIT)
+ if (TARGET_CPU_ZARCH)
insn = emit_insn_after (gen_pool_end_64 (), insn);
else
insn = emit_insn_after (gen_pool_end_31 (), insn);
@@ -4380,9 +4380,9 @@
/* We need correct insn addresses. */
shorten_branches (get_insns ());
- /* In 64-bit, we use a LARL to load the pool register. The pool is
+ /* On zSeries, we use a LARL to load the pool register. The pool is
located in the .rodata section, so we emit it after the function. */
- if (TARGET_64BIT)
+ if (TARGET_CPU_ZARCH)
{
insn = gen_main_base_64 (base_reg, pool->label);
insn = emit_insn_after (insn, pool->pool_insn);
@@ -4396,7 +4396,7 @@
s390_dump_pool (pool, 0);
}
- /* In 31-bit, if the total size of the function's code plus literal pool
+ /* On S/390, if the total size of the function's code plus literal pool
does not exceed 4096 bytes, we use BASR to set up a function base
pointer, and emit the literal pool at the end of the function. */
else if (INSN_ADDRESSES (INSN_UID (get_last_insn ()))
@@ -4496,7 +4496,7 @@
rtx insn;
rtx (*gen_reload_base) (rtx, rtx) =
- TARGET_64BIT? gen_reload_base_64 : gen_reload_base_31;
+ TARGET_CPU_ZARCH? gen_reload_base_64 : gen_reload_base_31;
/* We need correct insn addresses. */
@@ -4562,7 +4562,7 @@
|| INSN_ADDRESSES (INSN_UID (insn)) == -1)
continue;
- if (TARGET_64BIT)
+ if (TARGET_CPU_ZARCH)
{
if (curr_pool->size < S390_POOL_CHUNK_MAX)
continue;
@@ -5426,7 +5426,7 @@
SYMBOL_REF_FLAGS (got_symbol) = SYMBOL_FLAG_LOCAL;
}
- if (TARGET_64BIT)
+ if (TARGET_CPU_ZARCH)
{
rtx insn = emit_move_insn (pic_offset_table_rtx, got_symbol);
if (maybe_dead)
@@ -6583,7 +6583,7 @@
rtx x ATTRIBUTE_UNUSED,
unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
{
- if (TARGET_64BIT)
+ if (TARGET_CPU_ZARCH)
readonly_data_section ();
else
function_section (current_function_decl);
@@ -6629,7 +6629,7 @@
}
/* Operand 1 is the 'this' pointer. */
- if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function))))
+ if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
op[1] = gen_rtx_REG (Pmode, 3);
else
op[1] = gen_rtx_REG (Pmode, 2);
Index: gcc-3.4/gcc/config/s390/s390.md
diff -u gcc-3.4/gcc/config/s390/s390.md:1.2 gcc-3.4/gcc/config/s390/s390.md:1.3
--- gcc-3.4/gcc/config/s390/s390.md:1.2 Fri Jan 9 10:54:31 2004
+++ gcc-3.4/gcc/config/s390/s390.md Thu Feb 5 10:05:46 2004
@@ -429,8 +429,7 @@
(compare (and:DI (match_operand:DI 0 "memory_operand" "Q,S")
(match_operand:DI 1 "immediate_operand" "n,n"))
(match_operand:DI 2 "immediate_operand" "n,n")))]
- "TARGET_64BIT
- && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0))
+ "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0))
&& s390_single_qi (operands[1], DImode, 0) >= 0"
{
int part = s390_single_qi (operands[1], DImode, 0);
@@ -1237,7 +1236,7 @@
(define_insn "*movsi_lli"
[(set (match_operand:SI 0 "register_operand" "=d")
(match_operand:SI 1 "immediate_operand" "n"))]
- "TARGET_64BIT && s390_single_hi (operands[1], SImode, 0) >= 0
+ "TARGET_ZARCH && s390_single_hi (operands[1], SImode, 0) >= 0
&& !FP_REG_P (operands[0])"
{
int part = s390_single_hi (operands[1], SImode, 0);
@@ -1262,6 +1261,15 @@
[(set_attr "op_type" "RXY")
(set_attr "type" "la")])
+(define_insn "*movsi_larl"
+ [(set (match_operand:SI 0 "register_operand" "=d")
+ (match_operand:SI 1 "larl_operand" "X"))]
+ "!TARGET_64BIT && TARGET_CPU_ZARCH
+ && !FP_REG_P (operands[0])"
+ "larl\t%0,%1"
+ [(set_attr "op_type" "RIL")
+ (set_attr "type" "larl")])
+
(define_insn "*movsi"
[(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,T,!*f,!*f,!*f,!R,!T,?Q")
(match_operand:SI 1 "general_operand" "d,R,T,d,d,*f,R,T,*f,*f,?Q"))]
@@ -2356,14 +2364,14 @@
(define_insn "*extendqisi2"
[(set (match_operand:SI 0 "register_operand" "=d")
(sign_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
- "TARGET_64BIT && TARGET_LONG_DISPLACEMENT"
+ "TARGET_LONG_DISPLACEMENT"
"lb\t%0,%1"
[(set_attr "op_type" "RXY")])
(define_split
[(set (match_operand:SI 0 "register_operand" "")
(sign_extend:SI (match_operand:QI 1 "s_operand" "")))]
- "(!TARGET_64BIT || !TARGET_LONG_DISPLACEMENT) && !reload_completed"
+ "!TARGET_LONG_DISPLACEMENT && !reload_completed"
[(parallel
[(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_SETHIGH))
(clobber (reg:CC 33))])
@@ -2601,14 +2609,14 @@
(define_insn "*zero_extendqisi2_64"
[(set (match_operand:SI 0 "register_operand" "=d")
(zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
- "TARGET_64BIT"
+ "TARGET_ZARCH"
"llgc\t%0,%1"
[(set_attr "op_type" "RXY")])
(define_insn_and_split "*zero_extendqisi2_31"
[(set (match_operand:SI 0 "register_operand" "=&d")
(zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
- "!TARGET_64BIT"
+ "!TARGET_ZARCH"
"#"
"&& reload_completed"
[(set (match_dup 0) (const_int 0))
@@ -2623,7 +2631,7 @@
(define_expand "zero_extendqihi2"
[(set (match_operand:HI 0 "register_operand" "")
(zero_extend:HI (match_operand:QI 1 "register_operand" "")))]
- "TARGET_64BIT"
+ "TARGET_ZARCH"
"
{
operands[1] = gen_lowpart (HImode, operands[1]);
@@ -2635,14 +2643,14 @@
(define_insn "*zero_extendqihi2_64"
[(set (match_operand:HI 0 "register_operand" "=d")
(zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
- "TARGET_64BIT"
+ "TARGET_ZARCH"
"llgc\t%0,%1"
[(set_attr "op_type" "RXY")])
(define_insn_and_split "*zero_extendqihi2_31"
[(set (match_operand:HI 0 "register_operand" "=&d")
(zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
- "!TARGET_64BIT"
+ "!TARGET_ZARCH"
"#"
"&& reload_completed"
[(set (match_dup 0) (const_int 0))
@@ -4015,7 +4023,6 @@
[(set_attr "op_type" "RRE,RXY")
(set_attr "type" "imul")])
-
(define_insn "muldi3"
[(set (match_operand:DI 0 "register_operand" "=d,d,d")
(mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0")
@@ -4032,6 +4039,15 @@
; mulsi3 instruction pattern(s).
;
+(define_insn "*mulsi3_sign"
+ [(set (match_operand:SI 0 "register_operand" "=d")
+ (mult:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R"))
+ (match_operand:SI 1 "register_operand" "0")))]
+ ""
+ "mh\t%0,%2"
+ [(set_attr "op_type" "RX")
+ (set_attr "type" "imul")])
+
(define_insn "mulsi3"
[(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
(mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
@@ -4049,37 +4065,34 @@
; mulsidi3 instruction pattern(s).
;
-(define_expand "mulsidi3"
- [(set (match_operand:DI 0 "register_operand" "")
- (mult:DI (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" ""))
- (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" ""))))]
+(define_insn "mulsidi3"
+ [(set (match_operand:DI 0 "register_operand" "=d,d")
+ (mult:DI (sign_extend:DI
+ (match_operand:SI 1 "register_operand" "%0,0"))
+ (sign_extend:DI
+ (match_operand:SI 2 "nonimmediate_operand" "d,R"))))]
"!TARGET_64BIT"
-{
- rtx insn;
-
- emit_insn (gen_zero_extendsidi2 (operands[0], operands[1]));
- insn = emit_insn (gen_mulsi_6432 (operands[0], operands[0], operands[2]));
+ "@
+ mr\t%0,%2
+ m\t%0,%2"
+ [(set_attr "op_type" "RR,RX")
+ (set_attr "type" "imul")])
- REG_NOTES (insn) =
- gen_rtx_EXPR_LIST (REG_EQUAL,
- gen_rtx_MULT (DImode,
- gen_rtx_SIGN_EXTEND (DImode, operands[1]),
- gen_rtx_SIGN_EXTEND (DImode, operands[2])),
- REG_NOTES (insn));
- DONE;
-})
+;
+; umulsidi3 instruction pattern(s).
+;
-(define_insn "mulsi_6432"
- [(set (match_operand:DI 0 "register_operand" "=d,d")
- (mult:DI (sign_extend:DI
- (truncate:SI (match_operand:DI 1 "register_operand" "0,0")))
- (sign_extend:DI
- (match_operand:SI 2 "nonimmediate_operand" "d,R"))))]
- "!TARGET_64BIT"
- "@
- mr\t%0,%2
- m\t%0,%2"
- [(set_attr "op_type" "RR,RX")
+(define_insn "umulsidi3"
+ [(set (match_operand:DI 0 "register_operand" "=d,d")
+ (mult:DI (zero_extend:DI
+ (match_operand:SI 1 "register_operand" "%0,0"))
+ (zero_extend:DI
+ (match_operand:SI 2 "nonimmediate_operand" "d,m"))))]
+ "!TARGET_64BIT && TARGET_CPU_ZARCH"
+ "@
+ mlr\t%0,%2
+ ml\t%0,%2"
+ [(set_attr "op_type" "RRE,RXY")
(set_attr "type" "imul")])
;
@@ -4214,30 +4227,20 @@
(define_expand "divmoddi4"
[(parallel [(set (match_operand:DI 0 "general_operand" "")
- (div:DI (match_operand:DI 1 "general_operand" "")
+ (div:DI (match_operand:DI 1 "register_operand" "")
(match_operand:DI 2 "general_operand" "")))
(set (match_operand:DI 3 "general_operand" "")
(mod:DI (match_dup 1) (match_dup 2)))])
(clobber (match_dup 4))]
"TARGET_64BIT"
{
- rtx insn, div_equal, mod_equal, equal;
+ rtx insn, div_equal, mod_equal;
div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]);
mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]);
- equal = gen_rtx_IOR (TImode,
- gen_rtx_ZERO_EXTEND (TImode, div_equal),
- gen_rtx_ASHIFT (TImode,
- gen_rtx_ZERO_EXTEND (TImode, mod_equal),
- GEN_INT (64)));
operands[4] = gen_reg_rtx(TImode);
- emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4]));
- emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]);
- emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx);
- insn = emit_insn (gen_divmodtidi3 (operands[4], operands[4], operands[2]));
- REG_NOTES (insn) =
- gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
+ emit_insn (gen_divmodtidi3 (operands[4], operands[1], operands[2]));
insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
REG_NOTES (insn) =
@@ -4254,11 +4257,11 @@
[(set (match_operand:TI 0 "register_operand" "=d,d")
(ior:TI
(zero_extend:TI
- (div:DI (truncate:DI (match_operand:TI 1 "register_operand" "0,0"))
+ (div:DI (match_operand:DI 1 "register_operand" "0,0")
(match_operand:DI 2 "general_operand" "d,m")))
(ashift:TI
(zero_extend:TI
- (mod:DI (truncate:DI (match_dup 1))
+ (mod:DI (match_dup 1)
(match_dup 2)))
(const_int 64))))]
"TARGET_64BIT"
@@ -4272,11 +4275,11 @@
[(set (match_operand:TI 0 "register_operand" "=d,d")
(ior:TI
(zero_extend:TI
- (div:DI (truncate:DI (match_operand:TI 1 "register_operand" "0,0"))
+ (div:DI (match_operand:DI 1 "register_operand" "0,0")
(sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "d,m"))))
(ashift:TI
(zero_extend:TI
- (mod:DI (truncate:DI (match_dup 1))
+ (mod:DI (match_dup 1)
(sign_extend:DI (match_dup 2))))
(const_int 64))))]
"TARGET_64BIT"
@@ -4410,13 +4413,69 @@
; udivsi3 and umodsi3 instruction pattern(s).
;
+(define_expand "udivmodsi4"
+ [(parallel [(set (match_operand:SI 0 "general_operand" "")
+ (udiv:SI (match_operand:SI 1 "general_operand" "")
+ (match_operand:SI 2 "nonimmediate_operand" "")))
+ (set (match_operand:SI 3 "general_operand" "")
+ (umod:SI (match_dup 1) (match_dup 2)))])
+ (clobber (match_dup 4))]
+ "!TARGET_64BIT && TARGET_CPU_ZARCH"
+{
+ rtx insn, div_equal, mod_equal, equal;
+
+ div_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
+ mod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
+ equal = gen_rtx_IOR (DImode,
+ gen_rtx_ZERO_EXTEND (DImode, div_equal),
+ gen_rtx_ASHIFT (DImode,
+ gen_rtx_ZERO_EXTEND (DImode, mod_equal),
+ GEN_INT (32)));
+
+ operands[4] = gen_reg_rtx(DImode);
+ emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4]));
+ emit_move_insn (gen_lowpart (SImode, operands[4]), operands[1]);
+ emit_move_insn (gen_highpart (SImode, operands[4]), const0_rtx);
+ insn = emit_insn (gen_udivmoddisi3 (operands[4], operands[4], operands[2]));
+ REG_NOTES (insn) =
+ gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
+
+ insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
+ REG_NOTES (insn) =
+ gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
+
+ insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
+ REG_NOTES (insn) =
+ gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
+
+ DONE;
+})
+
+(define_insn "udivmoddisi3"
+ [(set (match_operand:DI 0 "register_operand" "=d,d")
+ (ior:DI (zero_extend:DI
+ (truncate:SI
+ (udiv:DI (match_operand:DI 1 "register_operand" "0,0")
+ (zero_extend:DI
+ (match_operand:SI 2 "nonimmediate_operand" "d,m")))))
+ (ashift:DI
+ (zero_extend:DI
+ (truncate:SI
+ (umod:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))
+ (const_int 32))))]
+ "!TARGET_64BIT && TARGET_CPU_ZARCH"
+ "@
+ dlr\t%0,%2
+ dl\t%0,%2"
+ [(set_attr "op_type" "RRE,RXY")
+ (set_attr "type" "idiv")])
(define_expand "udivsi3"
[(set (match_operand:SI 0 "register_operand" "=d")
(udiv:SI (match_operand:SI 1 "general_operand" "")
(match_operand:SI 2 "general_operand" "")))
(clobber (match_dup 3))]
- "!TARGET_64BIT"
+ "!TARGET_64BIT && !TARGET_CPU_ZARCH"
{
rtx insn, udiv_equal, umod_equal, equal;
@@ -4507,7 +4566,7 @@
(umod:SI (match_operand:SI 1 "nonimmediate_operand" "")
(match_operand:SI 2 "nonimmediate_operand" "")))
(clobber (match_dup 3))]
- "!TARGET_64BIT"
+ "!TARGET_64BIT && !TARGET_CPU_ZARCH"
{
rtx insn, udiv_equal, umod_equal, equal;
@@ -4787,7 +4846,7 @@
(and:SI (match_operand:SI 1 "nonimmediate_operand" "0")
(match_operand:SI 2 "immediate_operand" "n")))
(clobber (reg:CC 33))]
- "TARGET_64BIT && s390_single_hi (operands[2], SImode, -1) >= 0"
+ "TARGET_ZARCH && s390_single_hi (operands[2], SImode, -1) >= 0"
{
int part = s390_single_hi (operands[2], SImode, -1);
operands[2] = GEN_INT (s390_extract_hi (operands[2], SImode, part));
@@ -4840,7 +4899,7 @@
(and:HI (match_operand:HI 1 "register_operand" "%0,0")
(match_operand:HI 2 "nonmemory_operand" "d,n")))
(clobber (reg:CC 33))]
- "TARGET_64BIT"
+ "TARGET_ZARCH"
"@
nr\t%0,%2
nill\t%0,%x2"
@@ -4882,7 +4941,7 @@
(and:QI (match_operand:QI 1 "register_operand" "%0,0")
(match_operand:QI 2 "nonmemory_operand" "d,n")))
(clobber (reg:CC 33))]
- "TARGET_64BIT"
+ "TARGET_ZARCH"
"@
nr\t%0,%2
nill\t%0,%b2"
@@ -5041,7 +5100,7 @@
(ior:SI (match_operand:SI 1 "nonimmediate_operand" "0")
(match_operand:SI 2 "immediate_operand" "n")))
(clobber (reg:CC 33))]
- "TARGET_64BIT && s390_single_hi (operands[2], SImode, 0) >= 0"
+ "TARGET_ZARCH && s390_single_hi (operands[2], SImode, 0) >= 0"
{
int part = s390_single_hi (operands[2], SImode, 0);
operands[2] = GEN_INT (s390_extract_hi (operands[2], SImode, part));
@@ -5094,7 +5153,7 @@
(ior:HI (match_operand:HI 1 "register_operand" "%0,0")
(match_operand:HI 2 "nonmemory_operand" "d,n")))
(clobber (reg:CC 33))]
- "TARGET_64BIT"
+ "TARGET_ZARCH"
"@
or\t%0,%2
oill\t%0,%x2"
@@ -5136,7 +5195,7 @@
(ior:QI (match_operand:QI 1 "register_operand" "%0,0")
(match_operand:QI 2 "nonmemory_operand" "d,n")))
(clobber (reg:CC 33))]
- "TARGET_64BIT"
+ "TARGET_ZARCH"
"@
or\t%0,%2
oill\t%0,%b2"
@@ -5733,7 +5792,7 @@
[(set (match_operand:SI 0 "register_operand" "=d,d")
(rotate:SI (match_operand:SI 1 "register_operand" "d,d")
(match_operand:SI 2 "nonmemory_operand" "J,a")))]
- "TARGET_64BIT"
+ "TARGET_CPU_ZARCH"
"@
rll\t%0,%1,%c2
rll\t%0,%1,0(%2)"
@@ -6164,7 +6223,7 @@
{
if (get_attr_length (insn) == 4)
return "j%C1\t%l0";
- else if (TARGET_64BIT)
+ else if (TARGET_CPU_ZARCH)
return "jg%C1\t%l0";
else
abort ();
@@ -6174,7 +6233,7 @@
(set (attr "length")
(cond [(lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
(const_int 4)
- (ne (symbol_ref "TARGET_64BIT") (const_int 0))
+ (ne (symbol_ref "TARGET_CPU_ZARCH") (const_int 0))
(const_int 6)
(eq (symbol_ref "flag_pic") (const_int 0))
(const_int 6)] (const_int 8)))])
@@ -6213,7 +6272,7 @@
{
if (get_attr_length (insn) == 4)
return "j%D1\t%l0";
- else if (TARGET_64BIT)
+ else if (TARGET_CPU_ZARCH)
return "jg%D1\t%l0";
else
abort ();
@@ -6223,7 +6282,7 @@
(set (attr "length")
(cond [(lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
(const_int 4)
- (ne (symbol_ref "TARGET_64BIT") (const_int 0))
+ (ne (symbol_ref "TARGET_CPU_ZARCH") (const_int 0))
(const_int 6)
(eq (symbol_ref "flag_pic") (const_int 0))
(const_int 6)] (const_int 8)))])
@@ -6332,7 +6391,7 @@
(set (attr "length")
(cond [(lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
(const_int 4)
- (ne (symbol_ref "TARGET_64BIT") (const_int 0))
+ (ne (symbol_ref "TARGET_CPU_ZARCH") (const_int 0))
(const_int 10)
(eq (symbol_ref "flag_pic") (const_int 0))
(const_int 6)] (const_int 8)))])
@@ -6473,7 +6532,7 @@
{
if (get_attr_length (insn) == 4)
return "j\t%l0";
- else if (TARGET_64BIT)
+ else if (TARGET_CPU_ZARCH)
return "jg\t%l0";
else
abort ();
@@ -6483,7 +6542,7 @@
(set (attr "length")
(cond [(lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
(const_int 4)
- (ne (symbol_ref "TARGET_64BIT") (const_int 0))
+ (ne (symbol_ref "TARGET_CPU_ZARCH") (const_int 0))
(const_int 6)
(eq (symbol_ref "flag_pic") (const_int 0))
(const_int 6)] (const_int 8)))])
@@ -6625,6 +6684,7 @@
(use (match_operand 2 "" ""))]
""
{
+ bool plt_call = false;
rtx insn;
/* Direct function calls need special treatment. */
@@ -6638,11 +6698,12 @@
{
sym = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, sym), UNSPEC_PLT);
sym = gen_rtx_CONST (Pmode, sym);
+ plt_call = true;
}
/* Unless we can use the bras(l) insn, force the
routine address into a register. */
- if (!TARGET_SMALL_EXEC && !TARGET_64BIT)
+ if (!TARGET_SMALL_EXEC && !TARGET_CPU_ZARCH)
{
if (flag_pic)
sym = legitimize_pic_address (sym, 0);
@@ -6656,6 +6717,11 @@
/* Emit insn. */
insn = emit_call_insn (gen_call_exp (operands[0], operands[1],
gen_rtx_REG (Pmode, RETURN_REGNUM)));
+
+ /* 31-bit PLT stubs use the GOT register implicitly. */
+ if (!TARGET_64BIT && plt_call)
+ use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
+
DONE;
})
@@ -6666,62 +6732,40 @@
""
"")
-(define_insn "brasl"
- [(call (mem:QI (match_operand:DI 0 "bras_sym_operand" "X"))
- (match_operand:SI 1 "const_int_operand" "n"))
- (clobber (match_operand:DI 2 "register_operand" "=r"))]
- "TARGET_64BIT"
- "brasl\t%2,%0"
- [(set_attr "op_type" "RIL")
- (set_attr "type" "jsr")])
-
-(define_insn "bras"
- [(call (mem:QI (match_operand:SI 0 "bras_sym_operand" "X"))
- (match_operand:SI 1 "const_int_operand" "n"))
- (clobber (match_operand:SI 2 "register_operand" "=r"))]
- "TARGET_SMALL_EXEC"
+(define_insn "*bras"
+ [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
+ (match_operand 1 "const_int_operand" "n"))
+ (clobber (match_operand 2 "register_operand" "=r"))]
+ "TARGET_SMALL_EXEC && GET_MODE (operands[2]) == Pmode"
"bras\t%2,%0"
[(set_attr "op_type" "RI")
(set_attr "type" "jsr")])
-(define_insn "basr_64"
- [(call (mem:QI (match_operand:DI 0 "register_operand" "a"))
- (match_operand:SI 1 "const_int_operand" "n"))
- (clobber (match_operand:DI 2 "register_operand" "=r"))]
- "TARGET_64BIT"
- "basr\t%2,%0"
- [(set_attr "op_type" "RR")
- (set_attr "type" "jsr")
- (set_attr "atype" "agen")])
-
-(define_insn "basr_31"
- [(call (mem:QI (match_operand:SI 0 "register_operand" "a"))
- (match_operand:SI 1 "const_int_operand" "n"))
- (clobber (match_operand:SI 2 "register_operand" "=r"))]
- "!TARGET_64BIT"
- "basr\t%2,%0"
- [(set_attr "op_type" "RR")
- (set_attr "type" "jsr")
- (set_attr "atype" "agen")])
-
-(define_insn "bas_64"
- [(call (mem:QI (match_operand:QI 0 "address_operand" "U"))
- (match_operand:SI 1 "const_int_operand" "n"))
- (clobber (match_operand:DI 2 "register_operand" "=r"))]
- "TARGET_64BIT"
- "bas\t%2,%a0"
- [(set_attr "op_type" "RX")
- (set_attr "type" "jsr")])
-
-(define_insn "bas_31"
- [(call (mem:QI (match_operand:QI 0 "address_operand" "U"))
- (match_operand:SI 1 "const_int_operand" "n"))
- (clobber (match_operand:SI 2 "register_operand" "=r"))]
- "!TARGET_64BIT"
- "bas\t%2,%a0"
- [(set_attr "op_type" "RX")
+(define_insn "*brasl"
+ [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
+ (match_operand 1 "const_int_operand" "n"))
+ (clobber (match_operand 2 "register_operand" "=r"))]
+ "TARGET_CPU_ZARCH && GET_MODE (operands[2]) == Pmode"
+ "brasl\t%2,%0"
+ [(set_attr "op_type" "RIL")
(set_attr "type" "jsr")])
+(define_insn "*basr"
+ [(call (mem:QI (match_operand 0 "address_operand" "U"))
+ (match_operand 1 "const_int_operand" "n"))
+ (clobber (match_operand 2 "register_operand" "=r"))]
+ "GET_MODE (operands[2]) == Pmode"
+{
+ if (get_attr_op_type (insn) == OP_TYPE_RR)
+ return "basr\t%2,%0";
+ else
+ return "bas\t%2,%a0";
+}
+ [(set (attr "op_type")
+ (if_then_else (match_operand 0 "register_operand" "")
+ (const_string "RR") (const_string "RX")))
+ (set_attr "type" "jsr")
+ (set_attr "atype" "agen")])
;
; call_value instruction pattern(s).
@@ -6734,6 +6778,7 @@
(use (match_operand 3 "" ""))]
""
{
+ bool plt_call = false;
rtx insn;
/* Direct function calls need special treatment. */
@@ -6747,11 +6792,12 @@
{
sym = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, sym), UNSPEC_PLT);
sym = gen_rtx_CONST (Pmode, sym);
+ plt_call = true;
}
/* Unless we can use the bras(l) insn, force the
routine address into a register. */
- if (!TARGET_SMALL_EXEC && !TARGET_64BIT)
+ if (!TARGET_SMALL_EXEC && !TARGET_CPU_ZARCH)
{
if (flag_pic)
sym = legitimize_pic_address (sym, 0);
@@ -6766,6 +6812,11 @@
insn = emit_call_insn (
gen_call_value_exp (operands[0], operands[1], operands[2],
gen_rtx_REG (Pmode, RETURN_REGNUM)));
+
+ /* 31-bit PLT stubs use the GOT register implicitly. */
+ if (!TARGET_64BIT && plt_call)
+ use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
+
DONE;
})
@@ -6777,68 +6828,43 @@
""
"")
-(define_insn "brasl_r"
+(define_insn "*bras_r"
[(set (match_operand 0 "register_operand" "=df")
- (call (mem:QI (match_operand:DI 1 "bras_sym_operand" "X"))
+ (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
(match_operand:SI 2 "const_int_operand" "n")))
- (clobber (match_operand:DI 3 "register_operand" "=r"))]
- "TARGET_64BIT"
- "brasl\t%3,%1"
- [(set_attr "op_type" "RIL")
- (set_attr "type" "jsr")])
-
-(define_insn "bras_r"
- [(set (match_operand 0 "register_operand" "=df")
- (call (mem:QI (match_operand:SI 1 "bras_sym_operand" "X"))
- (match_operand:SI 2 "const_int_operand" "n")))
- (clobber (match_operand:SI 3 "register_operand" "=r"))]
- "TARGET_SMALL_EXEC"
+ (clobber (match_operand 3 "register_operand" "=r"))]
+ "TARGET_SMALL_EXEC && GET_MODE (operands[3]) == Pmode"
"bras\t%3,%1"
[(set_attr "op_type" "RI")
(set_attr "type" "jsr")])
-(define_insn "basr_r_64"
- [(set (match_operand 0 "register_operand" "=df")
- (call (mem:QI (match_operand:DI 1 "register_operand" "a"))
- (match_operand:SI 2 "const_int_operand" "n")))
- (clobber (match_operand:DI 3 "register_operand" "=r"))]
- "TARGET_64BIT"
- "basr\t%3,%1"
- [(set_attr "op_type" "RR")
- (set_attr "type" "jsr")
- (set_attr "atype" "agen")])
-
-(define_insn "basr_r_31"
+(define_insn "*brasl_r"
[(set (match_operand 0 "register_operand" "=df")
- (call (mem:QI (match_operand:SI 1 "register_operand" "a"))
- (match_operand:SI 2 "const_int_operand" "n")))
- (clobber (match_operand:SI 3 "register_operand" "=r"))]
- "!TARGET_64BIT"
- "basr\t%3,%1"
- [(set_attr "op_type" "RR")
- (set_attr "type" "jsr")
- (set_attr "atype" "agen")])
-
-(define_insn "bas_r_64"
- [(set (match_operand 0 "register_operand" "=df")
- (call (mem:QI (match_operand:QI 1 "address_operand" "U"))
- (match_operand:SI 2 "const_int_operand" "n")))
- (clobber (match_operand:DI 3 "register_operand" "=r"))]
- "TARGET_64BIT"
- "bas\t%3,%a1"
- [(set_attr "op_type" "RX")
+ (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
+ (match_operand 2 "const_int_operand" "n")))
+ (clobber (match_operand 3 "register_operand" "=r"))]
+ "TARGET_CPU_ZARCH && GET_MODE (operands[3]) == Pmode"
+ "brasl\t%3,%1"
+ [(set_attr "op_type" "RIL")
(set_attr "type" "jsr")])
-(define_insn "bas_r_31"
+(define_insn "*basr_r"
[(set (match_operand 0 "register_operand" "=df")
- (call (mem:QI (match_operand:QI 1 "address_operand" "U"))
- (match_operand:SI 2 "const_int_operand" "n")))
- (clobber (match_operand:SI 3 "register_operand" "=r"))]
- "!TARGET_64BIT"
- "bas\t%3,%a1"
- [(set_attr "op_type" "RX")
- (set_attr "type" "jsr")])
-
+ (call (mem:QI (match_operand 1 "address_operand" "U"))
+ (match_operand 2 "const_int_operand" "n")))
+ (clobber (match_operand 3 "register_operand" "=r"))]
+ "GET_MODE (operands[3]) == Pmode"
+{
+ if (get_attr_op_type (insn) == OP_TYPE_RR)
+ return "basr\t%3,%1";
+ else
+ return "bas\t%3,%a1";
+}
+ [(set (attr "op_type")
+ (if_then_else (match_operand 1 "register_operand" "")
+ (const_string "RR") (const_string "RX")))
+ (set_attr "type" "jsr")
+ (set_attr "atype" "agen")])
;;
;;- Thread-local storage support.
@@ -6922,7 +6948,7 @@
/* Unless we can use the bras(l) insn, force the
routine address into a register. */
- if (!TARGET_SMALL_EXEC && !TARGET_64BIT)
+ if (!TARGET_SMALL_EXEC && !TARGET_CPU_ZARCH)
{
if (flag_pic)
sym = legitimize_pic_address (sym, 0);
@@ -6956,74 +6982,46 @@
""
"")
-(define_insn "brasl_tls"
- [(set (match_operand 0 "register_operand" "=df")
- (call (mem:QI (match_operand:DI 1 "bras_sym_operand" "X"))
- (match_operand:SI 2 "const_int_operand" "n")))
- (clobber (match_operand:DI 3 "register_operand" "=r"))
- (use (match_operand:DI 4 "" ""))]
- "TARGET_64BIT"
- "brasl\t%3,%1%J4"
- [(set_attr "op_type" "RIL")
- (set_attr "type" "jsr")])
-
-(define_insn "bras_tls"
+(define_insn "*bras_tls"
[(set (match_operand 0 "register_operand" "=df")
- (call (mem:QI (match_operand:SI 1 "bras_sym_operand" "X"))
- (match_operand:SI 2 "const_int_operand" "n")))
- (clobber (match_operand:SI 3 "register_operand" "=r"))
- (use (match_operand:SI 4 "" ""))]
- "TARGET_SMALL_EXEC"
+ (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
+ (match_operand 2 "const_int_operand" "n")))
+ (clobber (match_operand 3 "register_operand" "=r"))
+ (use (match_operand 4 "" ""))]
+ "TARGET_SMALL_EXEC && GET_MODE (operands[3]) == Pmode"
"bras\t%3,%1%J4"
[(set_attr "op_type" "RI")
(set_attr "type" "jsr")])
-(define_insn "basr_tls_64"
+(define_insn "*brasl_tls"
[(set (match_operand 0 "register_operand" "=df")
- (call (mem:QI (match_operand:DI 1 "register_operand" "a"))
- (match_operand:SI 2 "const_int_operand" "n")))
- (clobber (match_operand:DI 3 "register_operand" "=r"))
- (use (match_operand:DI 4 "" ""))]
- "TARGET_64BIT"
- "basr\t%3,%1%J4"
- [(set_attr "op_type" "RR")
+ (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
+ (match_operand 2 "const_int_operand" "n")))
+ (clobber (match_operand 3 "register_operand" "=r"))
+ (use (match_operand 4 "" ""))]
+ "TARGET_CPU_ZARCH && GET_MODE (operands[3]) == Pmode"
+ "brasl\t%3,%1%J4"
+ [(set_attr "op_type" "RIL")
(set_attr "type" "jsr")])
-(define_insn "basr_tls_31"
- [(set (match_operand 0 "register_operand" "=df")
- (call (mem:QI (match_operand:SI 1 "register_operand" "a"))
- (match_operand:SI 2 "const_int_operand" "n")))
- (clobber (match_operand:SI 3 "register_operand" "=r"))
- (use (match_operand:SI 4 "" ""))]
- "!TARGET_64BIT"
- "basr\t%3,%1%J4"
- [(set_attr "op_type" "RR")
- (set_attr "type" "jsr")
- (set_attr "atype" "agen")])
-
-(define_insn "bas_tls_64"
- [(set (match_operand 0 "register_operand" "=df")
- (call (mem:QI (match_operand:QI 1 "address_operand" "U"))
- (match_operand:SI 2 "const_int_operand" "n")))
- (clobber (match_operand:DI 3 "register_operand" "=r"))
- (use (match_operand:DI 4 "" ""))]
- "TARGET_64BIT"
- "bas\t%3,%a1%J4"
- [(set_attr "op_type" "RX")
- (set_attr "type" "jsr")
- (set_attr "atype" "agen")])
-
-(define_insn "bas_tls_31"
+(define_insn "*basr_tls"
[(set (match_operand 0 "register_operand" "=df")
- (call (mem:QI (match_operand:QI 1 "address_operand" "U"))
- (match_operand:SI 2 "const_int_operand" "n")))
- (clobber (match_operand:SI 3 "register_operand" "=r"))
- (use (match_operand:SI 4 "" ""))]
- "!TARGET_64BIT"
- "bas\t%3,%a1%J4"
- [(set_attr "op_type" "RX")
- (set_attr "type" "jsr")
- (set_attr "atype" "agen")])
+ (call (mem:QI (match_operand 1 "address_operand" "U"))
+ (match_operand 2 "const_int_operand" "n")))
+ (clobber (match_operand 3 "register_operand" "=r"))
+ (use (match_operand 4 "" ""))]
+ "GET_MODE (operands[3]) == Pmode"
+{
+ if (get_attr_op_type (insn) == OP_TYPE_RR)
+ return "basr\t%3,%1%J4";
+ else
+ return "bas\t%3,%a1%J4";
+}
+ [(set (attr "op_type")
+ (if_then_else (match_operand 1 "register_operand" "")
+ (const_string "RR") (const_string "RX")))
+ (set_attr "type" "jsr")
+ (set_attr "atype" "agen")])
;;
;;- Miscellaneous instructions.
@@ -7207,52 +7205,52 @@
(define_insn "pool_start_31"
[(unspec_volatile [(const_int 0)] UNSPECV_POOL_START)]
- "!TARGET_64BIT"
+ "!TARGET_CPU_ZARCH"
".align\t4"
[(set_attr "op_type" "NN")
(set_attr "length" "2")])
(define_insn "pool_end_31"
[(unspec_volatile [(const_int 0)] UNSPECV_POOL_END)]
- "!TARGET_64BIT"
+ "!TARGET_CPU_ZARCH"
".align\t2"
[(set_attr "op_type" "NN")
(set_attr "length" "2")])
(define_insn "pool_start_64"
[(unspec_volatile [(const_int 0)] UNSPECV_POOL_START)]
- "TARGET_64BIT"
+ "TARGET_CPU_ZARCH"
".section\t.rodata\;.align\t8"
[(set_attr "op_type" "NN")
(set_attr "length" "0")])
(define_insn "pool_end_64"
[(unspec_volatile [(const_int 0)] UNSPECV_POOL_END)]
- "TARGET_64BIT"
+ "TARGET_CPU_ZARCH"
".previous"
[(set_attr "op_type" "NN")
(set_attr "length" "0")])
(define_insn "main_base_31_small"
- [(set (match_operand:SI 0 "register_operand" "=a")
- (unspec:SI [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
- "!TARGET_64BIT"
+ [(set (match_operand 0 "register_operand" "=a")
+ (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
+ "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
"basr\t%0,0"
[(set_attr "op_type" "RR")
(set_attr "type" "la")])
(define_insn "main_base_31_large"
- [(set (match_operand:SI 0 "register_operand" "=a")
- (unspec:SI [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))
+ [(set (match_operand 0 "register_operand" "=a")
+ (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))
(set (pc) (label_ref (match_operand 2 "" "")))]
- "!TARGET_64BIT"
+ "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
"bras\t%0,%2"
[(set_attr "op_type" "RI")])
(define_insn "main_base_64"
- [(set (match_operand:DI 0 "register_operand" "=a")
- (unspec:DI [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
- "TARGET_64BIT"
+ [(set (match_operand 0 "register_operand" "=a")
+ (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
+ "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
"larl\t%0,%1"
[(set_attr "op_type" "RIL")
(set_attr "type" "larl")])
@@ -7264,18 +7262,18 @@
[(set_attr "op_type" "NN")])
(define_insn "reload_base_31"
- [(set (match_operand:SI 0 "register_operand" "=a")
- (unspec:SI [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
- "!TARGET_64BIT"
+ [(set (match_operand 0 "register_operand" "=a")
+ (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
+ "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
"basr\t%0,0\;la\t%0,%1-.(%0)"
[(set_attr "op_type" "NN")
(set_attr "type" "la")
(set_attr "length" "6")])
(define_insn "reload_base_64"
- [(set (match_operand:DI 0 "register_operand" "=a")
- (unspec:DI [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
- "TARGET_64BIT"
+ [(set (match_operand 0 "register_operand" "=a")
+ (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
+ "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
"larl\t%0,%1"
[(set_attr "op_type" "RIL")
(set_attr "type" "larl")])
@@ -7302,24 +7300,15 @@
""
"s390_emit_epilogue (); DONE;")
-
-(define_insn "*return_si"
+(define_insn "*return"
[(return)
- (use (match_operand:SI 0 "register_operand" "a"))]
- "!TARGET_64BIT"
+ (use (match_operand 0 "register_operand" "a"))]
+ "GET_MODE (operands[0]) == Pmode"
"br\t%0"
[(set_attr "op_type" "RR")
(set_attr "type" "jsr")
(set_attr "atype" "agen")])
-(define_insn "*return_di"
- [(return)
- (use (match_operand:DI 0 "register_operand" "a"))]
- "TARGET_64BIT"
- "br\t%0"
- [(set_attr "op_type" "RR")
- (set_attr "type" "jsr")
- (set_attr "atype" "agen")])
;; Instruction definition to extend a 31-bit pointer into a 64-bit
;; pointer. This is used for compatability.
@@ -7327,7 +7316,7 @@
(define_expand "ptr_extend"
[(set (match_operand:DI 0 "register_operand" "=r")
(match_operand:SI 1 "register_operand" "r"))]
- ""
+ "TARGET_64BIT"
{
emit_insn (gen_anddi3 (operands[0],
gen_lowpart (DImode, operands[1]),
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