[llvm-commits] CVS: llvm/lib/CodeGen/RegAllocLinearScan.cpp

[Alkis Evlogimenos]

Changes in directory llvm/lib/CodeGen:

RegAllocLinearScan.cpp updated: 1.3 -> 1.4

---
Log message:

Print instructions before register allocation is performed.  Also fix
bug where spill instructions were added to the next basic block
instead of the end of the current one if the instruction that required
the spill was the last in the block.


---
Diffs of the changes:  (+26 -6)

Index: llvm/lib/CodeGen/RegAllocLinearScan.cpp
diff -u llvm/lib/CodeGen/RegAllocLinearScan.cpp:1.3 llvm/lib/CodeGen/RegAllocLinearScan.cpp:1.4
--- llvm/lib/CodeGen/RegAllocLinearScan.cpp:1.3	Sat Nov 29 23:15:36 2003
+++ llvm/lib/CodeGen/RegAllocLinearScan.cpp	Sun Nov 30 17:40:39 2003
@@ -203,6 +203,23 @@
     v2pMap_.clear();
     v2ssMap_.clear();
 
+    DEBUG(
+        for (MachineBasicBlockPtrs::iterator
+                 mbbi = mbbs_.begin(), mbbe = mbbs_.end();
+             mbbi != mbbe; ++mbbi) {
+            MachineBasicBlock* mbb = *mbbi;
+            std::cerr << mbb->getBasicBlock()->getName() << '\n';
+            for (MachineBasicBlock::iterator
+                     ii = mbb->begin(), ie = mbb->end();
+                 ii != ie; ++ii) {
+                MachineInstr* instr = *ii;
+                     
+                std::cerr << "\t";
+                instr->print(std::cerr, *tm_);
+            }
+        }
+        );
+
     // FIXME: this will work only for the X86 backend. I need to
     // device an algorthm to select the minimal (considering register
     // aliasing) number of temp registers to reserve so that we have 2
@@ -276,12 +293,6 @@
 
             DEBUG(std::cerr << "\tinstruction: ";
                   (*currentInstr_)->print(std::cerr, *tm_););
-            DEBUG(std::cerr << "\t\tspilling temporarily defined operands "
-                  "of previous instruction:\n");
-            for (unsigned i = 0, e = tempDefOperands_.size(); i != e; ++i) {
-                spillVirtReg(tempDefOperands_[i]);
-            }
-            tempDefOperands_.clear();
 
             // use our current mapping and actually replace and
             // virtual register with its allocated physical registers
@@ -422,6 +433,15 @@
                     (*currentInstr_)->SetMachineOperandReg(1, regA);
                 }
             }
+
+            DEBUG(std::cerr << "\t\tspilling temporarily defined operands "
+                  "of this instruction:\n");
+            ++currentInstr_; // we want to insert after this instruction
+            for (unsigned i = 0, e = tempDefOperands_.size(); i != e; ++i) {
+                spillVirtReg(tempDefOperands_[i]);
+            }
+            --currentInstr_; // restore currentInstr_ iterator
+            tempDefOperands_.clear();
         }
 
         for (unsigned i = 0, e = p2vMap_.size(); i != e; ++i) {