[llvm-commits] CVS: reopt/lib/LightWtProfiling/UnpackTraceFunction.cpp

Brian Gaeke gaeke at cs.uiuc.edu
Mon Oct 27 13:02:06 PST 2003


Changes in directory reopt/lib/LightWtProfiling:

UnpackTraceFunction.cpp updated: 1.5 -> 1.6

---
Log message:

Fix head-of-file ascii-art.
Extend tentacles into lib/Target/Sparc.
First try implementing insertBranchMachineInstrs().
Uncomment bits in containsReturnInstruction() which weren't compiling before.


---
Diffs of the changes:  (+66 -7)

Index: reopt/lib/LightWtProfiling/UnpackTraceFunction.cpp
diff -u reopt/lib/LightWtProfiling/UnpackTraceFunction.cpp:1.5 reopt/lib/LightWtProfiling/UnpackTraceFunction.cpp:1.6
--- reopt/lib/LightWtProfiling/UnpackTraceFunction.cpp:1.5	Thu Oct 23 18:34:42 2003
+++ reopt/lib/LightWtProfiling/UnpackTraceFunction.cpp	Mon Oct 27 13:01:16 2003
@@ -1,16 +1,19 @@
-//===- UnpackTraceFunction.cpp - Convert functions back to traces -*- C++ -*--=//
+//===- UnpackTraceFunction.cpp - Convert functions back to traces -*- C++ -*-=//
 //
 // WARNING, WARNING, WARNING; THIS IS HALF-UNIMPLEMENTED WORK IN PROGRESS!
 // Methods to convert functions, which had previously been converted from
 // traces into functions, back into traces.
 //
-//===-----------------------------------------------------------------------===//
+//===----------------------------------------------------------------------===//
 
 #include "../../../../lib/CodeGen/RegAlloc/AllocInfo.h"
+#include "../../../../lib/Target/Sparc/SparcInternals.h"
 #include "llvm/CodeGen/MachineBasicBlock.h"
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineInstr.h"
 #include "llvm/Function.h"
+#include "reopt/ScratchMemory.h"
+#include "Support/Debug.h"
 #include <set>
 
 // FIXME: following decl should be shared with TraceToFunction.cpp in a header
@@ -29,8 +32,64 @@
 /// replaceMachineCodeForFunction() would emit, to branch from the end
 /// of B to TargetAddr.
 ///
-void insertBranchMachineInstrs (void *TargetAddr, MachineBasicBlock &B) {
-  // FIXME: not yet implemented
+/// FIXME: refactor this so it shares code with SparcV9CodeEmitter.cpp's
+/// JITResolver::insertJumpAtAddr(), JITResolver::insertFarJumpAtAddr()
+///
+void insertBranchMachineInstrs (void *TargetPointer, MachineBasicBlock &B) {
+  int64_t Target = (int64_t)(intptr_t)TargetPointer;
+  DEBUG(std::cerr << "Emitting a jump to 0x" << std::hex << Target << "\n");
+
+  // FIXME: How do we know where this branch is going to end up in
+  // memory? For now, let's take a wild guess by saying it's at the
+  // beginning of the trace cache. Once we have a TraceCache
+  // MachineCodeEmitter, we should be able to ask it for
+  // getCurrentPCValue() for a much closer value (but not exactly
+  // right; we'll have to really fix this later.)
+  const int64_t Addr = (int64_t)(intptr_t)dummyFunction2;
+
+  int64_t BranchTarget = (Target-Addr) >> 2;
+  if (BranchTarget >= (1 << 19) || BranchTarget <= -(1 << 19)) {
+    /// FAR JUMP
+    static const unsigned 
+      o6 = SparcIntRegClass::o6, g0 = SparcIntRegClass::g0,
+      g1 = SparcIntRegClass::g1, g5 = SparcIntRegClass::g5;
+
+    MachineInstr* BinaryCode[] = {
+      // Get address to branch into %g1, using %g5 as a temporary
+      //
+      // sethi %uhi(Target), %g5     ;; get upper 22 bits of Target into %g5
+      BuildMI(V9::SETHI, 2).addSImm(Target >> 42).addReg(g5),
+      // or %g5, %ulo(Target), %g5   ;; get 10 lower bits of upper word into %g5
+      BuildMI(V9::ORi, 3).addReg(g5).addSImm((Target >> 32) & 0x03ff).addReg(g5),
+      // sllx %g5, 32, %g5           ;; shift those 10 bits to the upper word
+      BuildMI(V9::SLLXi6, 3).addReg(g5).addSImm(32).addReg(g5),
+      // sethi %hi(Target), %g1      ;; extract bits 10-31 into the dest reg
+      BuildMI(V9::SETHI, 2).addSImm((Target >> 10) & 0x03fffff).addReg(g1),
+      // or %g5, %g1, %g1            ;; get upper word (in %g5) into %g1
+      BuildMI(V9::ORr, 3).addReg(g5).addReg(g1).addReg(g1),
+      // or %g1, %lo(Target), %g1    ;; get lowest 10 bits of Target into %g1
+      BuildMI(V9::ORi, 3).addReg(g1).addSImm(Target & 0x03ff).addReg(g1),
+      // jmpl %g1, %g0, %g0          ;; indirect branch on %g1
+      BuildMI(V9::JMPLRETr, 3).addReg(g1).addReg(g0).addReg(g0),
+      // nop                         ;; delay slot
+      BuildMI(V9::NOP, 0)
+    };
+
+    for (unsigned i=0, e=sizeof(BinaryCode)/sizeof(BinaryCode[0]); i!=e; ++i)
+      B.push_back (BinaryCode[i]);
+  } else {
+    /// NEAR JUMP: use "ba" instruction
+    // If the target function is close enough to fit into the 19bit disp of
+    // BA, we should use this version, as it's much cheaper to generate.
+
+    // ba <target>
+    MachineInstr *I = BuildMI(V9::BA, 1).addSImm(BranchTarget);
+    B.push_back (I);
+
+    // nop
+    I = BuildMI(V9::NOP, 0);
+    B.push_back (I);
+  }
 }
 
 /// Get the register number or stack position where V can be found in the
@@ -52,14 +111,14 @@
 }
 
 /// Returns a pointer to the return instruction in B, if B contains one,
-/// or null otherwise. FIXME: SPARC target-specific.
+/// or null otherwise. FIXME: SPARC target-specific, and not done.
 ///
 const MachineInstr *containsReturnInstruction (MachineBasicBlock &B) {
   for (MachineBasicBlock::const_reverse_iterator i = B.rbegin (),
          e = B.rend (); i != e; ++i) {
     const MachineInstr *MI = *i;
-    /* if (MI->getOpcode () == SparcV9::JMPLRETi )
-      return MI; */
+    if (MI->getOpcode () == V9::JMPLRETi)
+      return MI;
   }
   return 0;
 }





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