[llvm-commits] CVS: llvm/lib/Target/X86/Makefile X86RegisterInfo.cpp X86RegisterInfo.h X86RegisterInfo.def
Chris Lattner
lattner at cs.uiuc.edu
Mon Aug 4 00:02:45 PDT 2003
Changes in directory llvm/lib/Target/X86:
Makefile updated: 1.1 -> 1.2
X86RegisterInfo.cpp updated: 1.32 -> 1.33
X86RegisterInfo.h updated: 1.14 -> 1.15
X86RegisterInfo.def (r1.14) removed
---
Log message:
Switch over to TableGen generated register file description
---
Diffs of the changes:
Index: llvm/lib/Target/X86/Makefile
diff -u llvm/lib/Target/X86/Makefile:1.1 llvm/lib/Target/X86/Makefile:1.2
--- llvm/lib/Target/X86/Makefile:1.1 Fri Oct 25 17:55:53 2002
+++ llvm/lib/Target/X86/Makefile Sun Aug 3 10:48:14 2003
@@ -2,3 +2,20 @@
LIBRARYNAME = x86
include $(LEVEL)/Makefile.common
+
+
+# Make sure that tblgen is run, first thing.
+$(SourceDepend): X86GenRegisterInfo.h.inc X86GenRegisterNames.inc X86GenRegisterInfo.inc
+
+X86GenRegisterNames.inc: $(wildcard *.td) $(TBLGEN)
+ $(TBLGEN) X86.td -gen-register-enums -o $@
+
+X86GenRegisterInfo.h.inc: $(wildcard *.td) $(TBLGEN)
+ $(TBLGEN) X86.td -gen-register-desc-header -o $@
+
+X86GenRegisterInfo.inc: $(wildcard *.td) $(TBLGEN)
+ $(TBLGEN) X86.td -gen-register-desc -o $@
+
+clean::
+ $(VERB) rm -f *.inc
+
Index: llvm/lib/Target/X86/X86RegisterInfo.cpp
diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.32 llvm/lib/Target/X86/X86RegisterInfo.cpp:1.33
--- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.32 Tue Jul 29 00:14:16 2003
+++ llvm/lib/Target/X86/X86RegisterInfo.cpp Sun Aug 3 10:48:14 2003
@@ -24,6 +24,9 @@
cl::desc("Disable frame pointer elimination optimization"));
}
+X86RegisterInfo::X86RegisterInfo()
+ : X86GenRegisterInfo(X86::ADJCALLSTACKDOWN, X86::ADJCALLSTACKUP) {}
+
static unsigned getIdx(const TargetRegisterClass *RC) {
switch (RC->getSize()) {
default: assert(0 && "Invalid data size!");
@@ -66,14 +69,6 @@
MBBI = MBB.insert(MBBI, MI)+1;
}
-const unsigned* X86RegisterInfo::getCalleeSaveRegs() const {
- static const unsigned CalleeSaveRegs[] = {
- X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
- };
- return CalleeSaveRegs;
-}
-
-
//===----------------------------------------------------------------------===//
// Stack Frame Processing methods
//===----------------------------------------------------------------------===//
@@ -249,103 +244,7 @@
}
}
-
-//===----------------------------------------------------------------------===//
-// Register Class Implementation Code
-//===----------------------------------------------------------------------===//
-
-//===----------------------------------------------------------------------===//
-// 8 Bit Integer Registers
-//
-namespace {
- const unsigned ByteRegClassRegs[] = {
- X86::AL, X86::CL, X86::DL, X86::BL, X86::AH, X86::CH, X86::DH, X86::BH,
- };
-
- TargetRegisterClass X86ByteRegisterClassInstance(1, 1, ByteRegClassRegs,
- ByteRegClassRegs+sizeof(ByteRegClassRegs)/sizeof(ByteRegClassRegs[0]));
-
-//===----------------------------------------------------------------------===//
-// 16 Bit Integer Registers
-//
- const unsigned ShortRegClassRegs[] = {
- X86::AX, X86::CX, X86::DX, X86::BX, X86::SI, X86::DI, X86::BP, X86::SP
- };
-
- struct R16CL : public TargetRegisterClass {
- R16CL():TargetRegisterClass(2, 2, ShortRegClassRegs, ShortRegClassRegs+8) {}
- iterator allocation_order_end(MachineFunction &MF) const {
- if (hasFP(MF)) // Does the function dedicate EBP to being a frame ptr?
- return end()-2; // Don't allocate SP or BP
- else
- return end()-1; // Don't allocate SP
- }
- } X86ShortRegisterClassInstance;
-
-//===----------------------------------------------------------------------===//
-// 32 Bit Integer Registers
-//
- const unsigned IntRegClassRegs[] = {
- X86::EAX, X86::ECX, X86::EDX, X86::EBX,
- X86::ESI, X86::EDI, X86::EBP, X86::ESP
- };
-
- struct R32CL : public TargetRegisterClass {
- R32CL() : TargetRegisterClass(4, 4, IntRegClassRegs, IntRegClassRegs+8) {}
- iterator allocation_order_end(MachineFunction &MF) const {
- if (hasFP(MF)) // Does the function dedicate EBP to being a frame ptr?
- return end()-2; // Don't allocate ESP or EBP
- else
- return end()-1; // Don't allocate ESP
- }
- } X86IntRegisterClassInstance;
-
-//===----------------------------------------------------------------------===//
-// Pseudo Floating Point Registers
-//
- const unsigned PFPRegClassRegs[] = {
-#define PFP(ENUM, NAME, FLAGS, TSFLAGS, ALIAS_SET) X86::ENUM,
-#include "X86RegisterInfo.def"
- };
-
- TargetRegisterClass X86FPRegisterClassInstance(10, 4, PFPRegClassRegs,
- PFPRegClassRegs+sizeof(PFPRegClassRegs)/sizeof(PFPRegClassRegs[0]));
-
-//===----------------------------------------------------------------------===//
-// Register class array...
-//
- const TargetRegisterClass * const X86RegClasses[] = {
- &X86ByteRegisterClassInstance,
- &X86ShortRegisterClassInstance,
- &X86IntRegisterClassInstance,
- &X86FPRegisterClassInstance,
- };
-}
-
-
-// Create static lists to contain register alias sets...
-#define ALIASLIST(NAME, ...) \
- static const unsigned NAME[] = { __VA_ARGS__ };
-#include "X86RegisterInfo.def"
-
-
-// X86Regs - Turn the X86RegisterInfo.def file into a bunch of register
-// descriptors
-//
-static const MRegisterDesc X86Regs[] = {
-#define R(ENUM, NAME, FLAGS, TSFLAGS, ALIAS_SET) \
- { NAME, ALIAS_SET, FLAGS, TSFLAGS },
-#include "X86RegisterInfo.def"
-};
-
-X86RegisterInfo::X86RegisterInfo()
- : MRegisterInfo(X86Regs, sizeof(X86Regs)/sizeof(X86Regs[0]),
- X86RegClasses,
- X86RegClasses+sizeof(X86RegClasses)/sizeof(X86RegClasses[0]),
- X86::ADJCALLSTACKDOWN, X86::ADJCALLSTACKUP) {
-}
-
-
+#include "X86GenRegisterInfo.inc"
const TargetRegisterClass*
X86RegisterInfo::getRegClassForType(const Type* Ty) const {
@@ -355,14 +254,14 @@
default: assert(0 && "Invalid type to getClass!");
case Type::BoolTyID:
case Type::SByteTyID:
- case Type::UByteTyID: return &X86ByteRegisterClassInstance;
+ case Type::UByteTyID: return &r8Instance;
case Type::ShortTyID:
- case Type::UShortTyID: return &X86ShortRegisterClassInstance;
+ case Type::UShortTyID: return &r16Instance;
case Type::IntTyID:
case Type::UIntTyID:
- case Type::PointerTyID: return &X86IntRegisterClassInstance;
+ case Type::PointerTyID: return &r32Instance;
case Type::FloatTyID:
- case Type::DoubleTyID: return &X86FPRegisterClassInstance;
+ case Type::DoubleTyID: return &rFPInstance;
}
}
Index: llvm/lib/Target/X86/X86RegisterInfo.h
diff -u llvm/lib/Target/X86/X86RegisterInfo.h:1.14 llvm/lib/Target/X86/X86RegisterInfo.h:1.15
--- llvm/lib/Target/X86/X86RegisterInfo.h:1.14 Thu Jul 31 22:48:42 2003
+++ llvm/lib/Target/X86/X86RegisterInfo.h Sun Aug 3 10:48:14 2003
@@ -11,11 +11,10 @@
class Type;
-struct X86RegisterInfo : public MRegisterInfo {
- X86RegisterInfo();
-
- const unsigned* getCalleeSaveRegs() const;
+#include "X86GenRegisterInfo.h.inc"
+struct X86RegisterInfo : public X86GenRegisterInfo {
+ X86RegisterInfo();
const TargetRegisterClass* getRegClassForType(const Type* Ty) const;
/// Code Generation virtual methods...
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