[llvm-commits] CVS: llvm/include/llvm/Reoptimizer/BinInterface/sparc9.h
Anand Shukla
ashukla at cs.uiuc.edu
Sat May 31 17:18:00 PDT 2003
Changes in directory llvm/include/llvm/Reoptimizer/BinInterface:
sparc9.h updated: 1.13 -> 1.14
---
Log message:
First version of working bininterface API/implementation
---
Diffs of the changes:
Index: llvm/include/llvm/Reoptimizer/BinInterface/sparc9.h
diff -u llvm/include/llvm/Reoptimizer/BinInterface/sparc9.h:1.13 llvm/include/llvm/Reoptimizer/BinInterface/sparc9.h:1.14
--- llvm/include/llvm/Reoptimizer/BinInterface/sparc9.h:1.13 Wed May 28 08:53:48 2003
+++ llvm/include/llvm/Reoptimizer/BinInterface/sparc9.h Sat May 31 17:16:52 2003
@@ -1,10 +1,8 @@
-//*****************************************************************************
-//
-// Portable SPARC v9 Machine Code Definition Header
+//===--------llvm/Reoptimizer/BinInterface/select.cpp-------------*- C++ -*--=//
//
+// Portable SPARC v9 Machine Code Definition Header
//
-// 2002 Cameron Buschardt
-//*****************************************************************************
+//===----------------------------------------------------------------------===//
//*****************************************************************************
// Register Names
@@ -48,7 +46,17 @@
#define R_SP R_O6
#define R_BP R_I6 // frame pointer
-extern char * reg_names[];
+#define BR_ANNUL 1
+#define BR_NOT_ANNUL 0
+#define BPR 3
+#define Bicc 2
+#define Bpcc 1
+#define FBfcc 6
+#define FBPfcc 5
+#define NOT_TAKEN_BR 0
+#define TAKEN_BR 1
+
+extern const char * reg_names[];
//*****************************************************************************
// Instruction bitfield definitions
@@ -97,6 +105,12 @@
#define INSTR_RS2 4:0
#define INSTR_RD 29:25
+#define INSTR_BRANCH_ANNUL 29:29
+#define INSTR_BPR_COND 27:25
+#define INSTR_INTBR_COND 28:25
+#define INSTR_BPR 24:22
+#define INSTR_INT_BR 24:22
+#define BR_PREDICT 19:19
#define RD_D16(i) ((RD_FLD(i, INSTR_D16HI) << 14) | RD_FLD(i, INSTR_D16LO))
@@ -114,7 +128,8 @@
//*****************************************************************************
#define OP2_ILLTRAP 0x00000000 /* 0b000 */ //OP=OP_BRANCH
#define OP2_NOP 0x00000004 /* 0b100 */ //BRANCH
-#define OP2_SETHI 0x00000004 /* 0b100 */ //BRANCH - uhh? duplicate? DOH =p
+#define OP2_SETHI 0x00000004 /* 0b100 */ //BRANCH - uhh? duplicate?
+ //DOH =p
#define OP2_BICC 0x00000002 /* 0b010 */
#define OP2_BPR 0x00000003 /* 0b011 */
#define OP2_FB 0x00000006 /* 0b110 */
@@ -176,9 +191,9 @@
// index is Condition code
//*****************************************************************************
-extern char * fcond_names[];
-extern char * icond_names[];
-extern char * rcond_names[];
+extern const char * fcond_names[];
+extern const char * icond_names[];
+extern const char * rcond_names[];
//*****************************************************************************
// Flag register encoding
@@ -191,7 +206,7 @@
#define FLAG_ICC 0x00000004 /* 0b100 */
#define FLAG_XCC 0x00000006 /* 0b110 */
-extern char * cc_names[];
+extern const char * cc_names[];
//*****************************************************************************
@@ -251,10 +266,10 @@
#define FCN_RETRY 1
//These masks are valid for the instructions below
-#define OPF_MASK_ONs 0x00000001 /* 0b0001 */ //these are valid for 'n' field
+#define OPF_MASK_ONs 0x00000001 /* 0b0001 */ //these are valid for 'n' field
#define OPF_MASK_ONd 0x00000002 /* 0b0010 */
#define OPF_MASK_ONq 0x00000003 /* 0b0011 */
-#define OPF_MASK_TOs 0x00000004 /* 0b0100 */ //these are valid for 't' field
+#define OPF_MASK_TOs 0x00000004 /* 0b0100 */ //these are valid for 't' field
#define OPF_MASK_TOd 0x00000008 /* 0b1000 */
#define OPF_MASK_TOq 0x0000000C /* 0b1100 */
@@ -296,18 +311,34 @@
#define OPF_FdMULq 0x0000006E /* 0b001101110 */
-#define OP3_FLUSH 0x0000003B /* 0b111011 */ //OP=OP_2 RS1 {I=0 -> rs2, I=1->simm13}
-#define OP3_FLUSHW 0x0000002B /* 0b101011 */ //OP=OP_2 I = 0
-#define OP3_JMPL 0x00000038 /* 0b111000 */ //OP=OP_2 RD, RS1 {I=0-> RS2, I=1->SIMM13}
-#define OP3_LDFA 0x00000030 /* 0b110000 */ //OP=OP_3 RD, Rs1, {I=0->IMM_ASI, RS2 I=1->SIMM13}
-#define OP3_LDDFA 0x00000033 /* 0b110011 */ //OP=OP_3 RD, Rs1, {I=0->IMM_ASI, RS2 I=1->SIMM13}
-#define OP3_LDQFA 0x00000032 /* 0b110010 */ //OP=OP_3 RD, Rs1, {I=0->IMM_ASI, RS2 I=1->SIMM13}
+#define OP3_FLUSH 0x0000003B /* 0b111011 */
+//OP=OP_2 RS1 {I=0 -> rs2, I=1->simm13}
+
+#define OP3_FLUSHW 0x0000002B /* 0b101011 */
+//OP=OP_2 I = 0
+
+#define OP3_JMPL 0x00000038 /* 0b111000 */
+//OP=OP_2 RD, RS1 {I=0-> RS2, I=1->SIMM13}
+
+#define OP3_LDFA 0x00000030 /* 0b110000 */
+//OP=OP_3 RD, Rs1, {I=0->IMM_ASI, RS2 I=1->SIMM13}
+
+#define OP3_LDDFA 0x00000033 /* 0b110011 */
+//OP=OP_3 RD, Rs1, {I=0->IMM_ASI, RS2 I=1->SIMM13}
+
+#define OP3_LDQFA 0x00000032 /* 0b110010 */
+//OP=OP_3 RD, Rs1, {I=0->IMM_ASI, RS2 I=1->SIMM13}
+
+#define OP3_LDSTUB 0x0000000D /* 0b001101 */
+//OP=OP_3 RD, Rs1 {I=0->RS2, I=1->SIMM13}
-#define OP3_LDSTUB 0x0000000D /* 0b001101 */ //OP=OP_3 RD, Rs1 {I=0->RS2, I=1->SIMM13}
#define OP3_STB 0x00000005 /* 0b000101 */
#define OP3_STH 0x00000006 /* 0b000110 */
#define OP3_STW 0x00000004 /* 0b000100 */
-#define OP3_STX 0x0000000E /* 0b001110 */ // Was 0b111 which is wrong (see pg 229 v9 spec)
+
+#define OP3_STD 0x00000007
+#define OP3_STX 0x0000000e /* 0b001110 */
+
#define OP3_LDSB 0x00000009 /* 0b001001 */
#define OP3_LDSH 0x0000000A /* 0b001010 */
#define OP3_LDSW 0x00000008 /* 0b001000 */
@@ -318,12 +349,16 @@
-#define OP3_LDSTUBA 0x0000001D /* 0b011101 */ //OP=OP_3 RD, RS1 {I=0->RS2, IMM_ASI, I=1->SIMM13}
+#define OP3_LDSTUBA 0x0000001D /* 0b011101 */
+//OP=OP_3 RD, RS1 {I=0->RS2, IMM_ASI, I=1->SIMM13}
-#define OP3_MEMBAR 0x00000028 /* 0b101000 */ //OP=OP_2 CMASK, MMASK //WTF?!?! some bits get set
+#define OP3_MEMBAR 0x00000028 /* 0b101000 */
+//OP=OP_2 CMASK, MMASK //WTF?!?! some bits get set
//These two instructions are FUNKY as hell
-#define OP3_FMOVcc 0x00000035 /* 0b110101 */ //OP=OP_2 RD, COND, OPF_CC, OPF_LOW, RS2
+#define OP3_FMOVcc 0x00000035 /* 0b110101 */
+//OP=OP_2 RD, COND, OPF_CC, OPF_LOW, RS2
+
#define OP3_MOVcc 0x0000002C /* 0b101100 */ //
@@ -395,100 +430,12 @@
MK_FLD(INSTR_I, 1) | \
MK_FLD(INSTR_OP3, OP3_ADD))
-// Add a register to a register
-#define MK_ADD_R_R(dreg, sreg1, sreg2) \
- (MK_FLD(INSTR_OP, OP_2) | \
- MK_FLD(INSTR_RD, dreg) | \
- MK_FLD(INSTR_OP3, OP3_ADD) | \
- MK_FLD(INSTR_RS1, sreg1) | \
- MK_FLD(INSTR_I, 0) | \
- MK_FLD(INSTR_RS2, sreg2))
-
-// Construct immediate-valued logical operation
-
-#define MK_LOGIC_IMM(op3, dreg, sreg, imm) \
- (MK_FLD(INSTR_OP, OP_2) | \
- MK_FLD(INSTR_RD, dreg) | \
- MK_FLD(INSTR_RS1, sreg) | \
- MK_FLD(INSTR_SIMM13, imm) | \
- MK_FLD(INSTR_I, 1) | \
- MK_FLD(INSTR_OP3, op3))
-
-// Construct reg-to-reg logical operation
-
-#define MK_LOGIC(op3, dreg, sreg1, sreg2) \
- (MK_FLD(INSTR_OP, OP_2) | \
- MK_FLD(INSTR_RD, dreg) | \
- MK_FLD(INSTR_RS1, sreg1) | \
- MK_FLD(INSTR_RS2, sreg2) | \
- MK_FLD(INSTR_I, 0) | \
- MK_FLD(INSTR_OP3, op3))
-
-// Construct sethi instruction
-
-#define MK_SETHI(dreg, imm) \
- (MK_FLD(INSTR_OP, OP_BRANCH) | \
- MK_FLD(INSTR_RD, dreg) | \
- MK_FLD(INSTR_OP2, OP2_SETHI) | \
- MK_FLD(INSTR_IMM22, imm))
-
-// Construct S{LL,RL,RA}X shift instruction.
-
-#define MK_SHIFTX(op3, dreg, sreg, shcnt) \
- (MK_FLD(INSTR_OP, OP_2) | \
- MK_FLD(INSTR_RD, dreg) | \
- MK_FLD(INSTR_OP3, op3) | \
- MK_FLD(INSTR_RS1, sreg) | \
- MK_FLD(INSTR_I, 1) | \
- MK_FLD(INSTR_X, 1) | \
- MK_FLD(INSTR_SHCNT64, shcnt))
-
-#define MK_STORE_IMM(srcreg, basereg, offset) \
- (MK_FLD(INSTR_OP, OP_3) | \
- MK_FLD(INSTR_RD, srcreg) | \
- MK_FLD(INSTR_OP3, OP3_STX) | \
- MK_FLD(INSTR_RS1, basereg) | \
- MK_FLD(INSTR_I, 1) | \
- MK_FLD(INSTR_SIMM13, offset))
-
-#define MK_LOAD_IMM(destreg, basereg, offset) \
- (MK_FLD(INSTR_OP, OP_3) | \
- MK_FLD(INSTR_RD, destreg) | \
- MK_FLD(INSTR_OP3, OP3_LDX) | \
- MK_FLD(INSTR_RS1, basereg) | \
- MK_FLD(INSTR_I, 1) | \
- MK_FLD(INSTR_SIMM13, offset))
-
-// Construct save instruction
-
-#define MK_SAVE_IMM(dreg, sreg, imm) \
- (MK_FLD(INSTR_OP, OP_2) | \
- MK_FLD(INSTR_RD, dreg) | \
- MK_FLD(INSTR_OP3, OP3_SAVE) | \
- MK_FLD(INSTR_RS1, sreg) | \
- MK_FLD(INSTR_I, 1) | \
- MK_FLD(INSTR_SIMM13, imm))
-
-#define MK_SAVE_REG(dreg, sreg1, sreg2) \
- (MK_FLD(INSTR_OP, OP_2) | \
- MK_FLD(INSTR_RD, dreg) | \
- MK_FLD(INSTR_OP3, OP3_SAVE) | \
- MK_FLD(INSTR_RS1, sreg1) | \
- MK_FLD(INSTR_I, 0) | \
- MK_FLD(INSTR_RS2, sreg2))
-
-#define MK_RESTORE_IMM(dreg, sreg, imm) \
- (MK_FLD(INSTR_OP, OP_2) | \
- MK_FLD(INSTR_RD, dreg) | \
- MK_FLD(INSTR_OP3, OP3_RESTORE) | \
- MK_FLD(INSTR_RS1, sreg) | \
- MK_FLD(INSTR_I, 1) | \
- MK_FLD(INSTR_SIMM13, imm))
-
-#define MK_JMPL_INDIRECT(dreg, sreg, imm) \
- (MK_FLD(INSTR_OP, OP_2) | \
- MK_FLD(INSTR_RD, dreg) | \
- MK_FLD(INSTR_OP3, OP3_JMPL) | \
- MK_FLD(INSTR_RS1, sreg) | \
- MK_FLD(INSTR_I, 1) | \
- MK_FLD(INSTR_SIMM13, imm))
+#define MK_INSTR_BRANCH_RS1(cond) \
+ (MK_FLD(INSTR_OP, OP_BRANCH) | \
+ MK_FLD(INSTR_BPR, BPR) | \
+ MK_FLD(INSTR_BPR_COND, cond))
+
+#define MK_INSTR_BRANCH_NO_RS1(cond) \
+ (MK_FLD(INSTR_OP, OP_BRANCH) | \
+ MK_FLD(INSTR_INT_BR, Bicc) | \
+ MK_FLD(INSTR_INTBR_COND, cond))
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