[llvm-commits] CVS: llvm/lib/Reoptimizer/Inst/lib/Phases.cpp SparcInstManip.cpp SparcInstManip.h
Joel Stanley
jstanley at cs.uiuc.edu
Sun May 18 20:36:01 PDT 2003
Changes in directory llvm/lib/Reoptimizer/Inst/lib:
Phases.cpp updated: 1.33 -> 1.34
SparcInstManip.cpp updated: 1.13 -> 1.14
SparcInstManip.h updated: 1.12 -> 1.13
---
Log message:
---
Diffs of the changes:
Index: llvm/lib/Reoptimizer/Inst/lib/Phases.cpp
diff -u llvm/lib/Reoptimizer/Inst/lib/Phases.cpp:1.33 llvm/lib/Reoptimizer/Inst/lib/Phases.cpp:1.34
--- llvm/lib/Reoptimizer/Inst/lib/Phases.cpp:1.33 Sun May 18 15:33:46 2003
+++ llvm/lib/Reoptimizer/Inst/lib/Phases.cpp Sun May 18 20:35:30 2003
@@ -190,14 +190,11 @@
if(m_excludeSet.find(i->first) == m_excludeSet.end()) {
// Function is not in exclude set, so go ahead and transform it
- // FIXME XXX TODO Get rid of this 'if' statement
- if(i->first == "fibs") {
- DEBUG_MSG(1, "Transforming function " << i->first
- << "[" << HEX(i->second.first)
- << ", " << HEX(i->second.second) << "]...\n");
-
- transformFunction(i->second);
- }
+ DEBUG_MSG(1, "Transforming function " << i->first
+ << "[" << HEX(i->second.first)
+ << ", " << HEX(i->second.second) << "]...\n");
+
+ transformFunction(i->second);
}
}
Index: llvm/lib/Reoptimizer/Inst/lib/SparcInstManip.cpp
diff -u llvm/lib/Reoptimizer/Inst/lib/SparcInstManip.cpp:1.13 llvm/lib/Reoptimizer/Inst/lib/SparcInstManip.cpp:1.14
--- llvm/lib/Reoptimizer/Inst/lib/SparcInstManip.cpp:1.13 Sun May 18 15:33:47 2003
+++ llvm/lib/Reoptimizer/Inst/lib/SparcInstManip.cpp Sun May 18 20:35:31 2003
@@ -11,7 +11,7 @@
//
// Phase 3 slot:
// +------------------------------------+
-// | save registers (new stack frame) |
+// | save regs; obtain new stack frame |
// | spill shared registers |
// | load Phase3Info addr to param1 |
// | call to phase 3 |
@@ -23,7 +23,7 @@
//
// Phase 4 slot:
// +---------------------------------------+
-// | save registers (new stack frame) |
+// | save regs; obtain new stack frame |
// | spill shared registers |
// | copy load-src addr to param1 |
// | load Phase4Info addr to param2 |
@@ -123,6 +123,11 @@
m_outputToInputReg[i] = i;
}
+static unsigned getSPSub(unsigned size)
+{
+ return MK_ADD_R_I(R_O6, R_O6, -size);
+}
+
void SparcInstManip::buildSlot(Phase3Info* p3info,
std::vector<unsigned>& snippet)
{
@@ -136,10 +141,14 @@
startCode(snippet);
generateSave();
- generateSpillShared(spillAddr);
+ generateSpillShared(spillAddr, REG_0, REG_1);
+
+ // Pass the p3info ptr to the phase 3 call
generateLoad((uint64_t) p3info, REG_0, REG_1);
+ generateStackStore(REG_0, PARAM_0);
generateCall((uint64_t) &phase3, slotBase);
- generateRestoreShared(spillAddr);
+
+ generateRestoreShared(spillAddr, REG_0, REG_1);
generateBranchAlways(p3info->getReplaceAddr(), slotBase, getRestoreInst());
endCode();
@@ -158,31 +167,37 @@
uint64_t spillAddr = (uint64_t) getPhase4SpillAddr();
const InstCandidate& cand = p4info->getCandidate();
- // NB: We pass parameters to the phase4 function in REG_0 and REG_1 on the assumption
- // that the input parameters will be looked for there. However, it is possible that
- // the input parameters will be taken from the parameter array at fixed offsets from
- // the stack pointer. Hence, we store the parameters there as well.
-
startCode(snippet);
generateSave();
+
+ // NB: Pass the value found in the register used by the candidate-load instruction,
+ // and the p4info ptr to the phase4 function call.
+
generateAddressCopy(cand.front().second, REG_0, true); // REG_0 live to call
generateStackStore(REG_0, PARAM_0);
generateSpillShared(spillAddr, REG_1, REG_2);
generateLoad((uint64_t) p4info, REG_1, REG_2); // REG_1 live to call
generateStackStore(REG_1, PARAM_1);
generateCall((uint64_t) &phase4, slotBase);
- generateRestoreShared(spillAddr);
+
+ generateRestoreShared(spillAddr, REG_0, REG_1);
generateBranchAlways(cand.front().first, slotBase, getRestoreInst());
endCode();
+
assert(snippet.size() == p4info->getSlotSize() &&
"Snippet size does not match expected slot size");
}
-static unsigned getSPSub(unsigned size)
+unsigned SparcInstManip::getAligned(unsigned value, unsigned align)
{
- return MK_ADD_R_I(R_O6, R_O6, -size);
+ // Round value up to the next multiple of align.
+ if(value % align != 0) {
+ value += align - (value % align);
+ }
+ assert(value % align == 0 && "Rounding computation failed (logic error?)");
+ return value;
}
void SparcInstManip::buildSlot(GBTElem* gbte,
@@ -195,14 +210,8 @@
// WORD_WIDTH * 3 belows occurs because we need two words for saving the values of the
// two scratch registers, and 1 word for saving the return address in the jump slot.
- unsigned stkSize = STKFRM_MIN + sharedSize + WORD_WIDTH * 3;
+ unsigned stkSize = getAligned(STKFRM_MIN + sharedSize + WORD_WIDTH * 3);
- if(stkSize % STACK_ALIGN != 0) {
- // Pad up to next multiple of STACK_ALIGN; assumes STACK_ALIGN % WORD_WIDTH == 0
- stkSize += WORD_WIDTH;
- assert(stkSize % STACK_ALIGN == 0 && "Alignment adjustment failed");
- }
-
DEBUG_MSG(2, "buildSlot(p5) stack offset is " << stkSize << endl);
unsigned retAddrStkOff = STKFRM_MIN + sharedSize + 2 * WORD_WIDTH;
@@ -265,6 +274,7 @@
return GEN_SAVE_SIZE +
GEN_SPL_SIZE +
+ GEN_STKSTORE_SIZE +
GEN_LOAD_SIZE +
GEN_CALL_SIZE +
GEN_UNSPL_SIZE +
@@ -279,7 +289,7 @@
(void) p3;
- return GEN_SAVE_SIZE +
+ return GEN_SAVE_SIZE +
getGenAddressCopySize(cand.front().second) +
GEN_STKSTORE_SIZE +
GEN_SPL_SIZE +
Index: llvm/lib/Reoptimizer/Inst/lib/SparcInstManip.h
diff -u llvm/lib/Reoptimizer/Inst/lib/SparcInstManip.h:1.12 llvm/lib/Reoptimizer/Inst/lib/SparcInstManip.h:1.13
--- llvm/lib/Reoptimizer/Inst/lib/SparcInstManip.h:1.12 Sun May 18 12:45:26 2003
+++ llvm/lib/Reoptimizer/Inst/lib/SparcInstManip.h Sun May 18 20:35:31 2003
@@ -91,14 +91,14 @@
void generateSave(unsigned offset = STKFRM_MIN);
void generateRestoreShared(uint64_t restoreFromAddr,
- LogicalRegister tmp1 = REG_0,
- LogicalRegister tmp2 = REG_1);
+ LogicalRegister tmp1,
+ LogicalRegister tmp2);
void generateRestoreShared(unsigned offset);
void generateSpillShared(uint64_t spillFromAddr,
- LogicalRegister tmp1 = REG_0,
- LogicalRegister tmp2 = REG_1);
+ LogicalRegister tmp1,
+ LogicalRegister tmp2);
void generateSpillShared(unsigned offset);
unsigned getRestoreInst() const;
@@ -123,6 +123,9 @@
uint64_t findNextStackLoad(uint64_t addr,
uint64_t end,
unsigned fpOffset);
+
+ unsigned getAligned(unsigned value,
+ unsigned align = STACK_ALIGN);
std::vector<unsigned>* m_pCurrSnippet;
GBTStackMap m_gbtStackMap; // Maps GBTElem* -> param address stack
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