[llvm-commits] CVS: llvm/lib/Target/Sparc/SparcInternals.h SparcOptInfo.cpp SparcRegClassInfo.h SparcRegInfo.cpp UltraSparcSchedInfo.cpp
Chris Lattner
lattner at cs.uiuc.edu
Sat Dec 28 21:14:20 PST 2002
Changes in directory llvm/lib/Target/Sparc:
SparcInternals.h updated: 1.76 -> 1.77
SparcOptInfo.cpp updated: 1.4 -> 1.5
SparcRegClassInfo.h updated: 1.14 -> 1.15
SparcRegInfo.cpp updated: 1.82 -> 1.83
UltraSparcSchedInfo.cpp updated: 1.2 -> 1.3
---
Log message:
More renamings of Target/Machine*Info to Target/Target*Info
---
Diffs of the changes:
Index: llvm/lib/Target/Sparc/SparcInternals.h
diff -u llvm/lib/Target/Sparc/SparcInternals.h:1.76 llvm/lib/Target/Sparc/SparcInternals.h:1.77
--- llvm/lib/Target/Sparc/SparcInternals.h:1.76 Sat Dec 28 20:50:33 2002
+++ llvm/lib/Target/Sparc/SparcInternals.h Sat Dec 28 21:13:02 2002
@@ -9,10 +9,10 @@
#define SPARC_INTERNALS_H
#include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/MachineSchedInfo.h"
+#include "llvm/Target/TargetSchedInfo.h"
#include "llvm/Target/TargetFrameInfo.h"
#include "llvm/Target/TargetCacheInfo.h"
-#include "llvm/Target/MachineRegInfo.h"
+#include "llvm/Target/TargetRegInfo.h"
#include "llvm/Target/TargetOptInfo.h"
#include "llvm/Type.h"
#include <sys/types.h>
@@ -211,11 +211,11 @@
//----------------------------------------------------------------------------
// class UltraSparcRegInfo
//
-// This class implements the virtual class MachineRegInfo for Sparc.
+// This class implements the virtual class TargetRegInfo for Sparc.
//
//----------------------------------------------------------------------------
-class UltraSparcRegInfo : public MachineRegInfo {
+class UltraSparcRegInfo : public TargetRegInfo {
// The actual register classes in the Sparc
//
enum RegClassIDs {
@@ -511,7 +511,7 @@
//---------------------------------------------------------------------------
-class UltraSparcSchedInfo: public MachineSchedInfo {
+class UltraSparcSchedInfo: public TargetSchedInfo {
public:
UltraSparcSchedInfo(const TargetMachine &tgt);
protected:
@@ -734,8 +734,8 @@
UltraSparc();
virtual const MachineInstrInfo &getInstrInfo() const { return instrInfo; }
- virtual const MachineSchedInfo &getSchedInfo() const { return schedInfo; }
- virtual const MachineRegInfo &getRegInfo() const { return regInfo; }
+ virtual const TargetSchedInfo &getSchedInfo() const { return schedInfo; }
+ virtual const TargetRegInfo &getRegInfo() const { return regInfo; }
virtual const TargetFrameInfo &getFrameInfo() const { return frameInfo; }
virtual const TargetCacheInfo &getCacheInfo() const { return cacheInfo; }
virtual const TargetOptInfo &getOptInfo() const { return optInfo; }
Index: llvm/lib/Target/Sparc/SparcOptInfo.cpp
diff -u llvm/lib/Target/Sparc/SparcOptInfo.cpp:1.4 llvm/lib/Target/Sparc/SparcOptInfo.cpp:1.5
--- llvm/lib/Target/Sparc/SparcOptInfo.cpp:1.4 Sun Oct 27 22:45:29 2002
+++ llvm/lib/Target/Sparc/SparcOptInfo.cpp Sat Dec 28 21:13:02 2002
@@ -5,7 +5,7 @@
//===----------------------------------------------------------------------===//
#include "SparcInternals.h"
-#include "llvm/Target/MachineRegInfo.h"
+#include "llvm/Target/TargetRegInfo.h"
#include "llvm/CodeGen/MachineInstr.h"
#include <stdlib.h>
Index: llvm/lib/Target/Sparc/SparcRegClassInfo.h
diff -u llvm/lib/Target/Sparc/SparcRegClassInfo.h:1.14 llvm/lib/Target/Sparc/SparcRegClassInfo.h:1.15
--- llvm/lib/Target/Sparc/SparcRegClassInfo.h:1.14 Mon Aug 12 16:25:04 2002
+++ llvm/lib/Target/Sparc/SparcRegClassInfo.h Sat Dec 28 21:13:02 2002
@@ -7,7 +7,7 @@
#ifndef SPARC_REG_CLASS_INFO_H
#define SPARC_REG_CLASS_INFO_H
-#include "llvm/Target/MachineRegInfo.h"
+#include "llvm/Target/TargetRegInfo.h"
#include "llvm/CodeGen/IGNode.h"
//-----------------------------------------------------------------------------
@@ -15,9 +15,9 @@
//-----------------------------------------------------------------------------
-struct SparcIntRegClass : public MachineRegClassInfo {
+struct SparcIntRegClass : public TargetRegClassInfo {
SparcIntRegClass(unsigned ID)
- : MachineRegClassInfo(ID, NumOfAvailRegs, NumOfAllRegs) { }
+ : TargetRegClassInfo(ID, NumOfAvailRegs, NumOfAllRegs) { }
void colorIGNode(IGNode *Node, std::vector<bool> &IsColorUsedArr) const;
@@ -73,12 +73,12 @@
// Float Register Class
//-----------------------------------------------------------------------------
-class SparcFloatRegClass : public MachineRegClassInfo {
+class SparcFloatRegClass : public TargetRegClassInfo {
int findFloatColor(const LiveRange *LR, unsigned Start,
unsigned End, std::vector<bool> &IsColorUsedArr) const;
public:
SparcFloatRegClass(unsigned ID)
- : MachineRegClassInfo(ID, NumOfAvailRegs, NumOfAllRegs) {}
+ : TargetRegClassInfo(ID, NumOfAvailRegs, NumOfAllRegs) {}
void colorIGNode(IGNode *Node, std::vector<bool> &IsColorUsedArr) const;
@@ -119,9 +119,9 @@
// allocated for two names.
//-----------------------------------------------------------------------------
-struct SparcIntCCRegClass : public MachineRegClassInfo {
+struct SparcIntCCRegClass : public TargetRegClassInfo {
SparcIntCCRegClass(unsigned ID)
- : MachineRegClassInfo(ID, 1, 2) { }
+ : TargetRegClassInfo(ID, 1, 2) { }
void colorIGNode(IGNode *Node, std::vector<bool> &IsColorUsedArr) const {
if (IsColorUsedArr[0])
@@ -149,9 +149,9 @@
// Only 4 Float CC registers are available
//-----------------------------------------------------------------------------
-struct SparcFloatCCRegClass : public MachineRegClassInfo {
+struct SparcFloatCCRegClass : public TargetRegClassInfo {
SparcFloatCCRegClass(unsigned ID)
- : MachineRegClassInfo(ID, 4, 4) { }
+ : TargetRegClassInfo(ID, 4, 4) { }
void colorIGNode(IGNode *Node, std::vector<bool> &IsColorUsedArr) const {
for(unsigned c = 0; c != 4; ++c)
Index: llvm/lib/Target/Sparc/SparcRegInfo.cpp
diff -u llvm/lib/Target/Sparc/SparcRegInfo.cpp:1.82 llvm/lib/Target/Sparc/SparcRegInfo.cpp:1.83
--- llvm/lib/Target/Sparc/SparcRegInfo.cpp:1.82 Sat Dec 28 14:21:29 2002
+++ llvm/lib/Target/Sparc/SparcRegInfo.cpp Sat Dec 28 21:13:02 2002
@@ -25,7 +25,7 @@
using std::vector;
UltraSparcRegInfo::UltraSparcRegInfo(const UltraSparc &tgt)
- : MachineRegInfo(tgt), NumOfIntArgRegs(6),
+ : TargetRegInfo(tgt), NumOfIntArgRegs(6),
NumOfFloatArgRegs(32), InvalidRegNum(1000) {
MachineRegClassArr.push_back(new SparcIntRegClass(IntRegClassID));
Index: llvm/lib/Target/Sparc/UltraSparcSchedInfo.cpp
diff -u llvm/lib/Target/Sparc/UltraSparcSchedInfo.cpp:1.2 llvm/lib/Target/Sparc/UltraSparcSchedInfo.cpp:1.3
--- llvm/lib/Target/Sparc/UltraSparcSchedInfo.cpp:1.2 Wed Aug 21 21:58:57 2002
+++ llvm/lib/Target/Sparc/UltraSparcSchedInfo.cpp Sat Dec 28 21:13:02 2002
@@ -700,12 +700,12 @@
// Purpose:
// Scheduling information for the UltraSPARC.
// Primarily just initializes machine-dependent parameters in
-// class MachineSchedInfo.
+// class TargetSchedInfo.
//---------------------------------------------------------------------------
/*ctor*/
UltraSparcSchedInfo::UltraSparcSchedInfo(const TargetMachine& tgt)
- : MachineSchedInfo(tgt,
+ : TargetSchedInfo(tgt,
(unsigned int) SPARC_NUM_SCHED_CLASSES,
SparcRUsageDesc,
SparcInstrUsageDeltas,
@@ -733,8 +733,8 @@
void
UltraSparcSchedInfo::initializeResources()
{
- // Compute MachineSchedInfo::instrRUsages and MachineSchedInfo::issueGaps
- MachineSchedInfo::initializeResources();
+ // Compute TargetSchedInfo::instrRUsages and TargetSchedInfo::issueGaps
+ TargetSchedInfo::initializeResources();
// Machine-dependent fixups go here. None for now.
}
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