[llvm-commits] CVS: llvm/lib/Target/Sparc/SparcInstr.def SparcInternals.h

[Chris Lattner]

Changes in directory llvm/lib/Target/Sparc:

SparcInstr.def updated: 1.13 -> 1.14
SparcInternals.h updated: 1.69 -> 1.70

---
Log message:

Remove all traces of the "Opcode Mask" field in the MachineInstr class



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Diffs of the changes:

Index: llvm/lib/Target/Sparc/SparcInstr.def
diff -u llvm/lib/Target/Sparc/SparcInstr.def:1.13 llvm/lib/Target/Sparc/SparcInstr.def:1.14
--- llvm/lib/Target/Sparc/SparcInstr.def:1.13	Thu Oct 24 20:43:26 2002
+++ llvm/lib/Target/Sparc/SparcInstr.def	Mon Oct 28 15:17:20 2002
@@ -52,14 +52,12 @@
 I(SETHI, "sethi",	2,  1, B22, false, 0,  1,  SPARC_IEUN,  M_INT_FLAG | M_LOGICAL_FLAG | M_ARITH_FLAG)
 
 // Add or add with carry.
-// Immed bit specifies if second operand is immediate(1) or register(0)
 I(ADD   , "add",	3,  2, B12, true , 0, 1, SPARC_IEUN,  M_INT_FLAG | M_ARITH_FLAG)
 I(ADDcc , "addcc",	4,  2, B12, true , 0, 1, SPARC_IEU1,  M_INT_FLAG | M_ARITH_FLAG | M_CC_FLAG )
 I(ADDC  , "addc",	3,  2, B12, true , 0, 1, SPARC_IEUN,  M_INT_FLAG | M_ARITH_FLAG)
 I(ADDCcc, "addccc",	4,  2, B12, true , 0, 1, SPARC_IEU1,  M_INT_FLAG | M_ARITH_FLAG | M_CC_FLAG )
 
 // Subtract or subtract with carry.
-// Immed bit specifies if second operand is immediate(1) or register(0)
 I(SUB   , "sub",	3,  2, B12, true , 0, 1, SPARC_IEUN,  M_INT_FLAG | M_ARITH_FLAG)
 I(SUBcc , "subcc",	4,  2, B12, true , 0, 1, SPARC_IEU1,  M_INT_FLAG | M_ARITH_FLAG | M_CC_FLAG )
 I(SUBC  , "subc",	3,  2, B12, true , 0, 1, SPARC_IEUN,  M_INT_FLAG | M_ARITH_FLAG)
@@ -157,8 +155,6 @@
 I(FITOQ, "fitoq",	2,  1,   0, false, 0, 0,  SPARC_FPA,  M_FLOAT_FLAG | M_INT_FLAG | M_ARITH_FLAG)
 
 // Branch on integer comparison with zero.
-// Annul bit specifies if intruction in delay slot is annulled(1) or not(0).
-// PredictTaken bit hints if branch should be predicted taken(1) or not(0).
 // Latency excludes the delay slot since it can be issued in same cycle.
 I(BRZ  , "brz", 	2, -1, B15, true , 1, 1,  SPARC_CTI,  M_INT_FLAG | M_BRANCH_FLAG)
 I(BRLEZ, "brlez",	2, -1, B15, true , 1, 1,  SPARC_CTI,  M_INT_FLAG | M_BRANCH_FLAG)
@@ -170,8 +166,6 @@
 // Branch on integer condition code.
 // The first argument specifies the ICC register: %icc or %xcc
 // Latency includes the delay slot.
-// Annul bit specifies if intruction in delay slot is annulled(1) or not(0).
-// PredictTaken bit hints if branch should be predicted taken(1) or not(0).
 I(BA  , "ba",		1, -1, B21, true , 1, 2,  SPARC_CTI,  M_CC_FLAG | M_BRANCH_FLAG)
 I(BN  , "bn",		2, -1, B21, true , 1, 2,  SPARC_CTI,  M_CC_FLAG | M_BRANCH_FLAG)
 I(BNE , "bne",		2, -1, B21, true , 1, 2,  SPARC_CTI,  M_CC_FLAG | M_BRANCH_FLAG)
@@ -190,8 +184,6 @@
 I(BVS , "bvs",		2, -1, B21, true , 1, 2,  SPARC_CTI,  M_CC_FLAG | M_BRANCH_FLAG)
 
 // Branch on floating point condition code.
-// Annul bit specifies if intruction in delay slot is annulled(1) or not(0).
-// PredictTaken bit hints if branch should be predicted taken(1) or not(0).
 // The first argument is the FCCn register (0 <= n <= 3).
 // Latency includes the delay slot.
 I(FBA  , "fba",		2, -1, B18, true , 1, 2,  SPARC_CTI,  M_CC_FLAG | M_BRANCH_FLAG)


Index: llvm/lib/Target/Sparc/SparcInternals.h
diff -u llvm/lib/Target/Sparc/SparcInternals.h:1.69 llvm/lib/Target/Sparc/SparcInternals.h:1.70
--- llvm/lib/Target/Sparc/SparcInternals.h:1.69	Sun Oct 27 19:03:43 2002
+++ llvm/lib/Target/Sparc/SparcInternals.h	Mon Oct 28 15:17:20 2002
@@ -22,13 +22,6 @@
 class PhyRegAlloc;
 class Pass;
 
-// OpCodeMask definitions for the Sparc V9
-// 
-const OpCodeMask	Immed		= 0x00002000; // immed or reg operand?
-const OpCodeMask	Annul		= 0x20000000; // annul delay instr?
-const OpCodeMask	PredictTaken	= 0x00080000; // predict branch taken?
-
-
 enum SparcInstrSchedClass {
   SPARC_NONE,		/* Instructions with no scheduling restrictions */
   SPARC_IEUN,		/* Integer class that can use IEU0 or IEU1 */