[llvm-commits] CVS: llvm/lib/CodeGen/InstrSched/InstrScheduling.cpp SchedGraph.cpp SchedGraph.h SchedPriorities.cpp
Chris Lattner
lattner at cs.uiuc.edu
Mon Oct 28 12:51:01 PST 2002
Changes in directory llvm/lib/CodeGen/InstrSched:
InstrScheduling.cpp updated: 1.47 -> 1.48
SchedGraph.cpp updated: 1.38 -> 1.39
SchedGraph.h updated: 1.24 -> 1.25
SchedPriorities.cpp updated: 1.22 -> 1.23
---
Log message:
Remove usage of MachineBasicBlock::get
---
Diffs of the changes:
Index: llvm/lib/CodeGen/InstrSched/InstrScheduling.cpp
diff -u llvm/lib/CodeGen/InstrSched/InstrScheduling.cpp:1.47 llvm/lib/CodeGen/InstrSched/InstrScheduling.cpp:1.48
--- llvm/lib/CodeGen/InstrSched/InstrScheduling.cpp:1.47 Sun Oct 27 22:53:02 2002
+++ llvm/lib/CodeGen/InstrSched/InstrScheduling.cpp Mon Oct 28 12:50:08 2002
@@ -628,16 +628,15 @@
// of the basic block, since they are not part of the schedule.
//
static void
-RecordSchedule(const BasicBlock* bb, const SchedulingManager& S)
+RecordSchedule(MachineBasicBlock &MBB, const SchedulingManager& S)
{
- MachineBasicBlock& mvec = MachineBasicBlock::get(bb);
const MachineInstrInfo& mii = S.schedInfo.getInstrInfo();
#ifndef NDEBUG
// Lets make sure we didn't lose any instructions, except possibly
// some NOPs from delay slots. Also, PHIs are not included in the schedule.
unsigned numInstr = 0;
- for (MachineBasicBlock::iterator I=mvec.begin(); I != mvec.end(); ++I)
+ for (MachineBasicBlock::iterator I=MBB.begin(); I != MBB.end(); ++I)
if (! mii.isNop((*I)->getOpCode()) &&
! mii.isDummyPhiInstr((*I)->getOpCode()))
++numInstr;
@@ -649,18 +648,18 @@
return; // empty basic block!
// First find the dummy instructions at the start of the basic block
- MachineBasicBlock::iterator I = mvec.begin();
- for ( ; I != mvec.end(); ++I)
+ MachineBasicBlock::iterator I = MBB.begin();
+ for ( ; I != MBB.end(); ++I)
if (! mii.isDummyPhiInstr((*I)->getOpCode()))
break;
- // Erase all except the dummy PHI instructions from mvec, and
+ // Erase all except the dummy PHI instructions from MBB, and
// pre-allocate create space for the ones we will put back in.
- mvec.erase(I, mvec.end());
+ MBB.erase(I, MBB.end());
InstrSchedule::const_iterator NIend = S.isched.end();
for (InstrSchedule::const_iterator NI = S.isched.begin(); NI != NIend; ++NI)
- mvec.push_back(const_cast<MachineInstr*>((*NI)->getMachineInstr()));
+ MBB.push_back(const_cast<MachineInstr*>((*NI)->getMachineInstr()));
}
@@ -1202,11 +1201,10 @@
// If not enough useful instructions were found, mark the NOPs to be used
// for filling delay slots, otherwise, otherwise just discard them.
//
-void
-ReplaceNopsWithUsefulInstr(SchedulingManager& S,
- SchedGraphNode* node,
- vector<SchedGraphNode*> sdelayNodeVec,
- SchedGraph* graph)
+static void ReplaceNopsWithUsefulInstr(SchedulingManager& S,
+ SchedGraphNode* node,
+ vector<SchedGraphNode*> sdelayNodeVec,
+ SchedGraph* graph)
{
vector<SchedGraphNode*> nopNodeVec; // this will hold unused NOPs
const MachineInstrInfo& mii = S.getInstrInfo();
@@ -1219,35 +1217,36 @@
// fill delay slots, otherwise, just discard them.
//
unsigned int firstDelaySlotIdx = node->getOrigIndexInBB() + 1;
- MachineBasicBlock& bbMvec = MachineBasicBlock::get(node->getBB());
- assert(bbMvec[firstDelaySlotIdx - 1] == brInstr &&
+ MachineBasicBlock& MBB = node->getMachineBasicBlock();
+ assert(MBB[firstDelaySlotIdx - 1] == brInstr &&
"Incorrect instr. index in basic block for brInstr");
// First find all useful instructions already in the delay slots
// and USE THEM. We'll throw away the unused alternatives below
//
for (unsigned i=firstDelaySlotIdx; i < firstDelaySlotIdx + ndelays; ++i)
- if (! mii.isNop(bbMvec[i]->getOpCode()))
+ if (! mii.isNop(MBB[i]->getOpCode()))
sdelayNodeVec.insert(sdelayNodeVec.begin(),
- graph->getGraphNodeForInstr(bbMvec[i]));
+ graph->getGraphNodeForInstr(MBB[i]));
// Then find the NOPs and keep only as many as are needed.
// Put the rest in nopNodeVec to be deleted.
for (unsigned i=firstDelaySlotIdx; i < firstDelaySlotIdx + ndelays; ++i)
- if (mii.isNop(bbMvec[i]->getOpCode()))
+ if (mii.isNop(MBB[i]->getOpCode()))
if (sdelayNodeVec.size() < ndelays)
- sdelayNodeVec.push_back(graph->getGraphNodeForInstr(bbMvec[i]));
+ sdelayNodeVec.push_back(graph->getGraphNodeForInstr(MBB[i]));
else
{
- nopNodeVec.push_back(graph->getGraphNodeForInstr(bbMvec[i]));
+ nopNodeVec.push_back(graph->getGraphNodeForInstr(MBB[i]));
//remove the MI from the Machine Code For Instruction
+ TerminatorInst *TI = MBB.getBasicBlock()->getTerminator();
MachineCodeForInstruction& llvmMvec =
- MachineCodeForInstruction::get((Instruction *)
- (node->getBB()->getTerminator()));
+ MachineCodeForInstruction::get((Instruction *)TI);
+
for(MachineCodeForInstruction::iterator mciI=llvmMvec.begin(),
mciE=llvmMvec.end(); mciI!=mciE; ++mciI){
- if(*mciI==bbMvec[i])
+ if (*mciI==MBB[i])
llvmMvec.erase(mciI);
}
}
@@ -1281,12 +1280,12 @@
// regalloc.
//
static void
-ChooseInstructionsForDelaySlots(SchedulingManager& S,
- const BasicBlock *bb,
+ChooseInstructionsForDelaySlots(SchedulingManager& S, MachineBasicBlock &MBB,
SchedGraph *graph)
{
const MachineInstrInfo& mii = S.getInstrInfo();
- const Instruction *termInstr = (Instruction*)bb->getTerminator();
+
+ Instruction *termInstr = (Instruction*)MBB.getBasicBlock()->getTerminator();
MachineCodeForInstruction &termMvec=MachineCodeForInstruction::get(termInstr);
vector<SchedGraphNode*> delayNodeVec;
const MachineInstr* brInstr = NULL;
@@ -1324,12 +1323,11 @@
// Simply passing in an empty delayNodeVec will have this effect.
//
delayNodeVec.clear();
- const MachineBasicBlock& bbMvec = MachineBasicBlock::get(bb);
- for (unsigned i=0; i < bbMvec.size(); ++i)
- if (bbMvec[i] != brInstr &&
- mii.getNumDelaySlots(bbMvec[i]->getOpCode()) > 0)
+ for (unsigned i=0; i < MBB.size(); ++i)
+ if (MBB[i] != brInstr &&
+ mii.getNumDelaySlots(MBB[i]->getOpCode()) > 0)
{
- SchedGraphNode* node = graph->getGraphNodeForInstr(bbMvec[i]);
+ SchedGraphNode* node = graph->getGraphNodeForInstr(MBB[i]);
ReplaceNopsWithUsefulInstr(S, node, delayNodeVec, graph);
}
}
@@ -1520,9 +1518,7 @@
GI != GE; ++GI)
{
SchedGraph* graph = (*GI);
- const vector<const BasicBlock*> &bbvec = graph->getBasicBlocks();
- assert(bbvec.size() == 1 && "Cannot schedule multiple basic blocks");
- const BasicBlock* bb = bbvec[0];
+ MachineBasicBlock &MBB = graph->getBasicBlock();
if (SchedDebugLevel >= Sched_PrintSchedTrace)
cerr << "\n*** TRACE OF INSTRUCTION SCHEDULING OPERATIONS\n\n";
@@ -1531,11 +1527,9 @@
SchedPriorities schedPrio(&F, graph,getAnalysis<FunctionLiveVarInfo>());
SchedulingManager S(target, graph, schedPrio);
- ChooseInstructionsForDelaySlots(S, bb, graph); // modifies graph
-
+ ChooseInstructionsForDelaySlots(S, MBB, graph); // modifies graph
ForwardListSchedule(S); // computes schedule in S
-
- RecordSchedule(bb, S); // records schedule in BB
+ RecordSchedule(MBB, S); // records schedule in BB
}
if (SchedDebugLevel >= Sched_PrintMachineCode)
Index: llvm/lib/CodeGen/InstrSched/SchedGraph.cpp
diff -u llvm/lib/CodeGen/InstrSched/SchedGraph.cpp:1.38 llvm/lib/CodeGen/InstrSched/SchedGraph.cpp:1.39
--- llvm/lib/CodeGen/InstrSched/SchedGraph.cpp:1.38 Sun Oct 27 22:45:24 2002
+++ llvm/lib/CodeGen/InstrSched/SchedGraph.cpp Mon Oct 28 12:50:08 2002
@@ -9,7 +9,7 @@
#include "SchedGraph.h"
#include "llvm/CodeGen/InstrSelection.h"
#include "llvm/CodeGen/MachineCodeForInstruction.h"
-#include "llvm/CodeGen/MachineBasicBlock.h"
+#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/Target/MachineRegInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/MachineInstrInfo.h"
@@ -27,7 +27,7 @@
// The following two types need to be classes, not typedefs, so we can use
// opaque declarations in SchedGraph.h
//
-struct RefVec: public vector< pair<SchedGraphNode*, int> > {
+struct RefVec: public vector<pair<SchedGraphNode*, int> > {
typedef vector< pair<SchedGraphNode*, int> >:: iterator iterator;
typedef vector< pair<SchedGraphNode*, int> >::const_iterator const_iterator;
};
@@ -135,23 +135,18 @@
//
/*ctor*/
-SchedGraphNode::SchedGraphNode(unsigned int _nodeId,
- const BasicBlock* _bb,
- const MachineInstr* _minstr,
+SchedGraphNode::SchedGraphNode(unsigned NID,
+ MachineBasicBlock *mbb,
int indexInBB,
- const TargetMachine& target)
- : nodeId(_nodeId),
- bb(_bb),
- minstr(_minstr),
- origIndexInBB(indexInBB),
- latency(0)
-{
+ const TargetMachine& Target)
+ : nodeId(NID), MBB(mbb), minstr(mbb ? (*mbb)[indexInBB] : 0),
+ origIndexInBB(indexInBB), latency(0) {
if (minstr)
{
MachineOpCode mopCode = minstr->getOpCode();
- latency = target.getInstrInfo().hasResultInterlock(mopCode)
- ? target.getInstrInfo().minLatency(mopCode)
- : target.getInstrInfo().maxLatency(mopCode);
+ latency = Target.getInstrInfo().hasResultInterlock(mopCode)
+ ? Target.getInstrInfo().minLatency(mopCode)
+ : Target.getInstrInfo().maxLatency(mopCode);
}
}
@@ -215,10 +210,8 @@
/*ctor*/
-SchedGraph::SchedGraph(const BasicBlock* bb,
- const TargetMachine& target)
-{
- bbVec.push_back(bb);
+SchedGraph::SchedGraph(MachineBasicBlock &mbb, const TargetMachine& target)
+ : MBB(mbb) {
buildGraph(target);
}
@@ -236,13 +229,9 @@
void
SchedGraph::dump() const
{
- cerr << " Sched Graph for Basic Blocks: ";
- for (unsigned i=0, N=bbVec.size(); i < N; i++)
- {
- cerr << (bbVec[i]->hasName()? bbVec[i]->getName() : "block")
- << " (" << bbVec[i] << ")"
- << ((i == N-1)? "" : ", ");
- }
+ cerr << " Sched Graph for Basic Block: ";
+ cerr << MBB.getBasicBlock()->getName()
+ << " (" << MBB.getBasicBlock() << ")";
cerr << "\n\n Actual Root nodes : ";
for (unsigned i=0, N=graphRoot->outEdges.size(); i < N; i++)
@@ -387,14 +376,12 @@
// Now add CD edges to the first branch instruction in the sequence from
// all preceding instructions in the basic block. Use 0 latency again.
//
- const BasicBlock* bb = firstBrNode->getBB();
- const MachineBasicBlock& mvec = MachineBasicBlock::get(bb);
- for (unsigned i=0, N=mvec.size(); i < N; i++)
+ for (unsigned i=0, N=MBB.size(); i < N; i++)
{
- if (mvec[i] == termMvec[first]) // reached the first branch
+ if (MBB[i] == termMvec[first]) // reached the first branch
break;
- SchedGraphNode* fromNode = this->getGraphNodeForInstr(mvec[i]);
+ SchedGraphNode* fromNode = this->getGraphNodeForInstr(MBB[i]);
if (fromNode == NULL)
continue; // dummy instruction, e.g., PHI
@@ -406,12 +393,12 @@
// the terminator) that also have delay slots, add an outgoing edge
// from the instruction to the instructions in the delay slots.
//
- unsigned d = mii.getNumDelaySlots(mvec[i]->getOpCode());
+ unsigned d = mii.getNumDelaySlots(MBB[i]->getOpCode());
assert(i+d < N && "Insufficient delay slots for instruction?");
for (unsigned j=1; j <= d; j++)
{
- SchedGraphNode* toNode = this->getGraphNodeForInstr(mvec[i+j]);
+ SchedGraphNode* toNode = this->getGraphNodeForInstr(MBB[i+j]);
assert(toNode && "No node for machine instr in delay slot?");
(void) new SchedGraphEdge(fromNode, toNode,
SchedGraphEdge::CtrlDep,
@@ -525,8 +512,6 @@
SchedGraph::addMachineRegEdges(RegToRefVecMap& regToRefVecMap,
const TargetMachine& target)
{
- assert(bbVec.size() == 1 && "Only handling a single basic block here");
-
// This assumes that such hardwired registers are never allocated
// to any LLVM value (since register allocation happens later), i.e.,
// any uses or defs of this register have been made explicit!
@@ -732,19 +717,17 @@
// Collect value defs. for implicit operands. The interface to extract
// them assumes they must be virtual registers!
//
- for (int i=0, N = (int) minstr.getNumImplicitRefs(); i < N; ++i)
+ for (unsigned i=0, N = minstr.getNumImplicitRefs(); i != N; ++i)
if (minstr.implicitRefIsDefined(i))
if (const Instruction* defInstr =
dyn_cast_or_null<Instruction>(minstr.getImplicitRef(i)))
- {
- valueToDefVecMap[defInstr].push_back(std::make_pair(node, -i));
- }
+ valueToDefVecMap[defInstr].push_back(std::make_pair(node, -i));
}
void
-SchedGraph::buildNodesforBB(const TargetMachine& target,
- const BasicBlock* bb,
+SchedGraph::buildNodesForBB(const TargetMachine& target,
+ MachineBasicBlock& MBB,
vector<SchedGraphNode*>& memNodeVec,
RegToRefVecMap& regToRefVecMap,
ValueToDefVecMap& valueToDefVecMap)
@@ -753,84 +736,21 @@
// Build graph nodes for each VM instruction and gather def/use info.
// Do both those together in a single pass over all machine instructions.
- const MachineBasicBlock& mvec = MachineBasicBlock::get(bb);
- for (unsigned i=0; i < mvec.size(); i++)
- if (! mii.isDummyPhiInstr(mvec[i]->getOpCode()))
- {
- SchedGraphNode* node = new SchedGraphNode(getNumNodes(), bb,
- mvec[i], i, target);
- this->noteGraphNodeForInstr(mvec[i], node);
-
- // Remember all register references and value defs
- findDefUseInfoAtInstr(target, node,
- memNodeVec, regToRefVecMap,valueToDefVecMap);
- }
-
-#undef REALLY_NEED_TO_SEARCH_SUCCESSOR_PHIS
-#ifdef REALLY_NEED_TO_SEARCH_SUCCESSOR_PHIS
- // This is a BIG UGLY HACK. IT NEEDS TO BE ELIMINATED.
- // Look for copy instructions inserted in this BB due to Phi instructions
- // in the successor BBs.
- // There MUST be exactly one copy per Phi in successor nodes.
- //
- for (BasicBlock::succ_const_iterator SI=bb->succ_begin(), SE=bb->succ_end();
- SI != SE; ++SI)
- for (BasicBlock::const_iterator PI=(*SI)->begin(), PE=(*SI)->end();
- PI != PE; ++PI)
- {
- if ((*PI)->getOpcode() != Instruction::PHINode)
- break; // No more Phis in this successor
-
- // Find the incoming value from block bb to block (*SI)
- int bbIndex = cast<PHINode>(*PI)->getBasicBlockIndex(bb);
- assert(bbIndex >= 0 && "But I know bb is a predecessor of (*SI)?");
- Value* inVal = cast<PHINode>(*PI)->getIncomingValue(bbIndex);
- assert(inVal != NULL && "There must be an in-value on every edge");
-
- // Find the machine instruction that makes a copy of inval to (*PI).
- // This must be in the current basic block (bb).
- const MachineCodeForVMInstr& mvec = MachineBasicBlock::get(*PI);
- const MachineInstr* theCopy = NULL;
- for (unsigned i=0; i < mvec.size() && theCopy == NULL; i++)
- if (! mii.isDummyPhiInstr(mvec[i]->getOpCode()))
- // not a Phi: assume this is a copy and examine its operands
- for (int o=0, N=(int) mvec[i]->getNumOperands(); o < N; o++)
- {
- const MachineOperand& mop = mvec[i]->getOperand(o);
-
- if (mvec[i]->operandIsDefined(o))
- assert(mop.getVRegValue() == (*PI) && "dest shd be my Phi");
-
- if (! mvec[i]->operandIsDefined(o) ||
- NOT NEEDED? mvec[i]->operandIsDefinedAndUsed(o))
- if (mop.getVRegValue() == inVal)
- { // found the copy!
- theCopy = mvec[i];
- break;
- }
- }
-
- // Found the dang instruction. Now create a node and do the rest...
- if (theCopy != NULL)
- {
- SchedGraphNode* node = new SchedGraphNode(getNumNodes(), bb,
- theCopy, origIndexInBB++, target);
- this->noteGraphNodeForInstr(theCopy, node);
- findDefUseInfoAtInstr(target, node,
- memNodeVec, regToRefVecMap,valueToDefVecMap);
- }
- }
-#endif //REALLY_NEED_TO_SEARCH_SUCCESSOR_PHIS
+ for (unsigned i=0; i < MBB.size(); i++)
+ if (!mii.isDummyPhiInstr(MBB[i]->getOpCode())) {
+ SchedGraphNode* node = new SchedGraphNode(getNumNodes(), &MBB, i, target);
+ noteGraphNodeForInstr(MBB[i], node);
+
+ // Remember all register references and value defs
+ findDefUseInfoAtInstr(target, node, memNodeVec, regToRefVecMap,
+ valueToDefVecMap);
+ }
}
void
SchedGraph::buildGraph(const TargetMachine& target)
{
- const BasicBlock* bb = bbVec[0];
-
- assert(bbVec.size() == 1 && "Only handling a single basic block here");
-
// Use this data structure to note all machine operands that compute
// ordinary LLVM values. These must be computed defs (i.e., instructions).
// Note that there may be multiple machine instructions that define
@@ -854,8 +774,8 @@
RegToRefVecMap regToRefVecMap;
// Make a dummy root node. We'll add edges to the real roots later.
- graphRoot = new SchedGraphNode(0, NULL, NULL, -1, target);
- graphLeaf = new SchedGraphNode(1, NULL, NULL, -1, target);
+ graphRoot = new SchedGraphNode(0, NULL, -1, target);
+ graphLeaf = new SchedGraphNode(1, NULL, -1, target);
//----------------------------------------------------------------
// First add nodes for all the machine instructions in the basic block
@@ -863,8 +783,8 @@
// Do this one VM instruction at a time since the SchedGraphNode needs that.
// Also, remember the load/store instructions to add memory deps later.
//----------------------------------------------------------------
-
- buildNodesforBB(target, bb, memNodeVec, regToRefVecMap, valueToDefVecMap);
+
+ buildNodesForBB(target, MBB, memNodeVec, regToRefVecMap, valueToDefVecMap);
//----------------------------------------------------------------
// Now add edges for the following (all are incoming edges except (4)):
@@ -882,21 +802,19 @@
//
//----------------------------------------------------------------
- MachineBasicBlock& bbMvec = MachineBasicBlock::get(bb);
-
// First, add edges to the terminator instruction of the basic block.
- this->addCDEdges(bb->getTerminator(), target);
+ this->addCDEdges(MBB.getBasicBlock()->getTerminator(), target);
// Then add memory dep edges: store->load, load->store, and store->store.
// Call instructions are treated as both load and store.
this->addMemEdges(memNodeVec, target);
// Then add edges between call instructions and CC set/use instructions
- this->addCallCCEdges(memNodeVec, bbMvec, target);
+ this->addCallCCEdges(memNodeVec, MBB, target);
// Then add incoming def-use (SSA) edges for each machine instruction.
- for (unsigned i=0, N=bbMvec.size(); i < N; i++)
- addEdgesForInstruction(*bbMvec[i], valueToDefVecMap, target);
+ for (unsigned i=0, N=MBB.size(); i < N; i++)
+ addEdgesForInstruction(*MBB[i], valueToDefVecMap, target);
#ifdef NEED_SEPARATE_NONSSA_EDGES_CODE
// Then add non-SSA edges for all VM instructions in the block.
@@ -955,8 +873,9 @@
SchedGraphSet::buildGraphsForMethod(const Function *F,
const TargetMachine& target)
{
- for (Function::const_iterator BI = F->begin(); BI != F->end(); ++BI)
- addGraph(new SchedGraph(BI, target));
+ MachineFunction &MF = MachineFunction::get(F);
+ for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I)
+ addGraph(new SchedGraph(*I, target));
}
Index: llvm/lib/CodeGen/InstrSched/SchedGraph.h
diff -u llvm/lib/CodeGen/InstrSched/SchedGraph.h:1.24 llvm/lib/CodeGen/InstrSched/SchedGraph.h:1.25
--- llvm/lib/CodeGen/InstrSched/SchedGraph.h:1.24 Sun Oct 27 18:26:50 2002
+++ llvm/lib/CodeGen/InstrSched/SchedGraph.h Mon Oct 28 12:50:08 2002
@@ -132,9 +132,8 @@
class SchedGraphNode: public NonCopyable {
-private:
- unsigned int nodeId;
- const BasicBlock* bb;
+ unsigned nodeId;
+ MachineBasicBlock *MBB;
const MachineInstr* minstr;
std::vector<SchedGraphEdge*> inEdges;
std::vector<SchedGraphEdge*> outEdges;
@@ -151,14 +150,14 @@
//
// Accessor methods
//
- unsigned int getNodeId () const { return nodeId; }
- const MachineInstr* getMachineInstr () const { return minstr; }
- const MachineOpCode getOpCode () const { return minstr->getOpCode();}
- int getLatency () const { return latency; }
- unsigned int getNumInEdges () const { return inEdges.size(); }
- unsigned int getNumOutEdges () const { return outEdges.size(); }
+ unsigned getNodeId () const { return nodeId; }
+ const MachineInstr* getMachineInstr () const { return minstr; }
+ const MachineOpCode getOpCode () const { return minstr->getOpCode(); }
+ int getLatency () const { return latency; }
+ unsigned getNumInEdges () const { return inEdges.size(); }
+ unsigned getNumOutEdges () const { return outEdges.size(); }
bool isDummyNode () const { return (minstr == NULL); }
- const BasicBlock* getBB () const { return bb; }
+ MachineBasicBlock &getMachineBasicBlock() const { return *MBB; }
int getOrigIndexInBB() const { return origIndexInBB; }
//
@@ -194,11 +193,10 @@
// disable default constructor and provide a ctor for single-block graphs
/*ctor*/ SchedGraphNode(); // DO NOT IMPLEMENT
- /*ctor*/ SchedGraphNode (unsigned int _nodeId,
- const BasicBlock* _bb,
- const MachineInstr* _minstr,
+ /*ctor*/ SchedGraphNode (unsigned nodeId,
+ MachineBasicBlock *mbb,
int indexInBB,
- const TargetMachine& _target);
+ const TargetMachine& Target);
/*dtor*/ ~SchedGraphNode ();
};
@@ -208,8 +206,7 @@
public NonCopyable,
private hash_map<const MachineInstr*, SchedGraphNode*>
{
-private:
- std::vector<const BasicBlock*> bbVec; // basic blocks included in the graph
+ MachineBasicBlock &MBB; // basic blocks for this graph
SchedGraphNode* graphRoot; // the root and leaf are not inserted
SchedGraphNode* graphLeaf; // in the hash_map (see getNumNodes())
@@ -222,8 +219,8 @@
//
// Accessor methods
//
- const std::vector<const BasicBlock*>& getBasicBlocks() const { return bbVec; }
- const unsigned int getNumNodes() const { return size()+2; }
+ MachineBasicBlock &getBasicBlock() const { return MBB; }
+ unsigned getNumNodes() const { return size()+2; }
SchedGraphNode* getRoot() const { return graphRoot; }
SchedGraphNode* getLeaf() const { return graphLeaf; }
@@ -272,8 +269,7 @@
friend class SchedGraphSet; // give access to ctor
// disable default constructor and provide a ctor for single-block graphs
- /*ctor*/ SchedGraph (); // DO NOT IMPLEMENT
- /*ctor*/ SchedGraph (const BasicBlock* bb,
+ /*ctor*/ SchedGraph (MachineBasicBlock &bb,
const TargetMachine& target);
/*dtor*/ ~SchedGraph ();
@@ -289,8 +285,8 @@
//
void buildGraph (const TargetMachine& target);
- void buildNodesforBB (const TargetMachine& target,
- const BasicBlock* bb,
+ void buildNodesForBB (const TargetMachine& target,
+ MachineBasicBlock &MBB,
std::vector<SchedGraphNode*>& memNod,
RegToRefVecMap& regToRefVecMap,
ValueToDefVecMap& valueToDefVecMap);
Index: llvm/lib/CodeGen/InstrSched/SchedPriorities.cpp
diff -u llvm/lib/CodeGen/InstrSched/SchedPriorities.cpp:1.22 llvm/lib/CodeGen/InstrSched/SchedPriorities.cpp:1.23
--- llvm/lib/CodeGen/InstrSched/SchedPriorities.cpp:1.22 Fri Aug 9 15:07:54 2002
+++ llvm/lib/CodeGen/InstrSched/SchedPriorities.cpp Mon Oct 28 12:50:08 2002
@@ -12,6 +12,7 @@
#include "SchedPriorities.h"
#include "llvm/Analysis/LiveVar/FunctionLiveVarInfo.h"
+#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/Support/CFG.h"
#include "Support/PostOrderIterator.h"
using std::cerr;
@@ -269,7 +270,7 @@
// else check if instruction is a last use and save it in the hash_map
bool hasLastUse = false;
- const BasicBlock* bb = graphNode->getBB();
+ const BasicBlock* bb = graphNode->getMachineBasicBlock().getBasicBlock();
const ValueSet &LVs = LVI.getLiveVarSetBeforeMInst(MI, bb);
for (MachineInstr::const_val_op_iterator OI = MI->begin(), OE = MI->end();
More information about the llvm-commits
mailing list