[llvm-commits] CVS: llvm/lib/CodeGen/InstrSched/InstrScheduling.cpp SchedGraph.cpp

[Chris Lattner]

Changes in directory llvm/lib/CodeGen/InstrSched:

InstrScheduling.cpp updated: 1.44 -> 1.45
SchedGraph.cpp updated: 1.35 -> 1.36

---
Log message:

Rename MachineCodeForBasicBlock to MachineBasicBlock



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Diffs of the changes:

Index: llvm/lib/CodeGen/InstrSched/InstrScheduling.cpp
diff -u llvm/lib/CodeGen/InstrSched/InstrScheduling.cpp:1.44 llvm/lib/CodeGen/InstrSched/InstrScheduling.cpp:1.45
--- llvm/lib/CodeGen/InstrSched/InstrScheduling.cpp:1.44	Sun Oct 27 18:26:50 2002
+++ llvm/lib/CodeGen/InstrSched/InstrScheduling.cpp	Sun Oct 27 19:41:17 2002
@@ -8,7 +8,7 @@
 #include "SchedPriorities.h"
 #include "llvm/CodeGen/MachineInstr.h"
 #include "llvm/CodeGen/MachineCodeForInstruction.h"
-#include "llvm/CodeGen/MachineCodeForBasicBlock.h"
+#include "llvm/CodeGen/MachineBasicBlock.h"
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/Analysis/LiveVar/FunctionLiveVarInfo.h" // FIXME: Remove when modularized better
 #include "llvm/Target/TargetMachine.h"
@@ -631,14 +631,14 @@
 static void
 RecordSchedule(const BasicBlock* bb, const SchedulingManager& S)
 {
-  MachineCodeForBasicBlock& mvec = MachineCodeForBasicBlock::get(bb);
+  MachineBasicBlock& mvec = MachineBasicBlock::get(bb);
   const MachineInstrInfo& mii = S.schedInfo.getInstrInfo();
   
 #ifndef NDEBUG
   // Lets make sure we didn't lose any instructions, except possibly
   // some NOPs from delay slots.  Also, PHIs are not included in the schedule.
   unsigned numInstr = 0;
-  for (MachineCodeForBasicBlock::iterator I=mvec.begin(); I != mvec.end(); ++I)
+  for (MachineBasicBlock::iterator I=mvec.begin(); I != mvec.end(); ++I)
     if (! mii.isNop((*I)->getOpCode()) &&
 	! mii.isDummyPhiInstr((*I)->getOpCode()))
       ++numInstr;
@@ -650,7 +650,7 @@
     return;				// empty basic block!
   
   // First find the dummy instructions at the start of the basic block
-  MachineCodeForBasicBlock::iterator I = mvec.begin();
+  MachineBasicBlock::iterator I = mvec.begin();
   for ( ; I != mvec.end(); ++I)
     if (! mii.isDummyPhiInstr((*I)->getOpCode()))
       break;
@@ -1220,7 +1220,7 @@
   // fill delay slots, otherwise, just discard them.
   //  
   unsigned int firstDelaySlotIdx = node->getOrigIndexInBB() + 1;
-  MachineCodeForBasicBlock& bbMvec = MachineCodeForBasicBlock::get(node->getBB());
+  MachineBasicBlock& bbMvec = MachineBasicBlock::get(node->getBB());
   assert(bbMvec[firstDelaySlotIdx - 1] == brInstr &&
          "Incorrect instr. index in basic block for brInstr");
   
@@ -1325,8 +1325,8 @@
   // Simply passing in an empty delayNodeVec will have this effect.
   // 
   delayNodeVec.clear();
-  const MachineCodeForBasicBlock& bbMvec = MachineCodeForBasicBlock::get(bb);
-  for (unsigned i=0; i < bbMvec.size(); i++)
+  const MachineBasicBlock& bbMvec = MachineBasicBlock::get(bb);
+  for (unsigned i=0; i < bbMvec.size(); ++i)
     if (bbMvec[i] != brInstr &&
         mii.getNumDelaySlots(bbMvec[i]->getOpCode()) > 0)
       {


Index: llvm/lib/CodeGen/InstrSched/SchedGraph.cpp
diff -u llvm/lib/CodeGen/InstrSched/SchedGraph.cpp:1.35 llvm/lib/CodeGen/InstrSched/SchedGraph.cpp:1.36
--- llvm/lib/CodeGen/InstrSched/SchedGraph.cpp:1.35	Sat Oct 12 19:39:22 2002
+++ llvm/lib/CodeGen/InstrSched/SchedGraph.cpp	Sun Oct 27 19:41:17 2002
@@ -9,7 +9,7 @@
 #include "SchedGraph.h"
 #include "llvm/CodeGen/InstrSelection.h"
 #include "llvm/CodeGen/MachineCodeForInstruction.h"
-#include "llvm/CodeGen/MachineCodeForBasicBlock.h"
+#include "llvm/CodeGen/MachineBasicBlock.h"
 #include "llvm/Target/MachineRegInfo.h"
 #include "llvm/Target/TargetMachine.h"
 #include "llvm/Function.h"
@@ -387,7 +387,7 @@
   // all preceding instructions in the basic block.  Use 0 latency again.
   // 
   const BasicBlock* bb = firstBrNode->getBB();
-  const MachineCodeForBasicBlock& mvec = MachineCodeForBasicBlock::get(bb);
+  const MachineBasicBlock& mvec = MachineBasicBlock::get(bb);
   for (unsigned i=0, N=mvec.size(); i < N; i++) 
     {
       if (mvec[i] == termMvec[first])   // reached the first branch
@@ -480,7 +480,7 @@
 // 
 void
 SchedGraph::addCallCCEdges(const vector<SchedGraphNode*>& memNodeVec,
-                           MachineCodeForBasicBlock& bbMvec,
+                           MachineBasicBlock& bbMvec,
                            const TargetMachine& target)
 {
   const MachineInstrInfo& mii = target.getInstrInfo();
@@ -753,7 +753,7 @@
   
   // Build graph nodes for each VM instruction and gather def/use info.
   // Do both those together in a single pass over all machine instructions.
-  const MachineCodeForBasicBlock& mvec = MachineCodeForBasicBlock::get(bb);
+  const MachineBasicBlock& mvec = MachineBasicBlock::get(bb);
   for (unsigned i=0; i < mvec.size(); i++)
     if (! mii.isDummyPhiInstr(mvec[i]->getOpCode()))
       {
@@ -789,7 +789,7 @@
         
         // Find the machine instruction that makes a copy of inval to (*PI).
         // This must be in the current basic block (bb).
-        const MachineCodeForVMInstr& mvec = MachineCodeForBasicBlock::get(*PI);
+        const MachineCodeForVMInstr& mvec = MachineBasicBlock::get(*PI);
         const MachineInstr* theCopy = NULL;
         for (unsigned i=0; i < mvec.size() && theCopy == NULL; i++)
           if (! mii.isDummyPhiInstr(mvec[i]->getOpCode()))
@@ -882,7 +882,7 @@
   // 
   //----------------------------------------------------------------
       
-  MachineCodeForBasicBlock& bbMvec = MachineCodeForBasicBlock::get(bb);
+  MachineBasicBlock& bbMvec = MachineBasicBlock::get(bb);
   
   // First, add edges to the terminator instruction of the basic block.
   this->addCDEdges(bb->getTerminator(), target);