<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/234223>234223</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            LLDB does not correctly apply register types to scalable registers (AArch64 SVE)
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            lldb
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          DavidSpickett
      </td>
    </tr>
</table>

<pre>
    Using the example code from https://github.com/llvm/llvm-project/issues/87471#issuecomment-5729159625a and running the program using qemu-aarch64, the types for SVE's `Z` register are only used when the vector length exactly matches the size of the types that QEMU initially sent.

Which is to be expected. We go to a lot of trouble to make sure the sizes match up and that's normally a good thing, but SVE vector length is a special case.
```
-> 17     if (prctl(PR_SVE_SET_VL, 256) == -1) {
<...>
(lldb) register read vg z0
  vg = 0x0000000000000008 # Vector length is 8*8=64 bytes.
  z0 = 0x00000<...>               # No register type used for z0. 
(lldb) n                          # Step over vector length change.
<...>
-> 22     asm volatile(
   23 SVE_REGS(INIT_Z)
<...>
(lldb) register read vg z0
  vg = 0x0000000000000020         # Vector length is now 32*8=256 bytes.
  z0 = 0x00<...>
     = {                          # The register type is used.
 q = {
```
LLDB trusts the value of `vg` over any size set in register XML, so we are always able to print registers, but the types are trusting the XML size.

QEMU describes them as:
```
<feature name="org.gnu.gdb.aarch64.sve">
  <vector id="svevqu" type="uint128" count="16"/>
  <vector id="svevqs" type="int128" count="16"/>
 <vector id="svevdf" type="ieee_double" count="32"/>
  <vector id="svevdu" type="uint64" count="32"/>
  <vector id="svevds" type="int64" count="32"/>
  <vector id="svevsf" type="ieee_single" count="64"/>
  <vector id="svevsu" type="uint32" count="64"/>
 <vector id="svevss" type="int32" count="64"/>
  <vector id="svevhf" type="ieee_half" count="128"/>
  <vector id="svevhu" type="uint16" count="128"/>
  <vector id="svevhs" type="int16" count="128"/>
 <vector id="svevbu" type="uint8" count="256"/>
  <vector id="svevbs" type="int8" count="256"/>
  <union id="svevnq">
    <field name="u" type="svevqu"/>
    <field name="s" type="svevqs"/>
  </union>
 <union id="svevnd">
    <field name="f" type="svevdf"/>
    <field name="u" type="svevdu"/>
    <field name="s" type="svevds"/>
 </union>
  <union id="svevns">
    <field name="f" type="svevsf"/>
 <field name="u" type="svevsu"/>
    <field name="s" type="svevss"/>
  </union>
  <union id="svevnh">
    <field name="f" type="svevhf"/>
    <field name="u" type="svevhu"/>
    <field name="s" type="svevhs"/>
  </union>
  <union id="svevnb">
    <field name="u" type="svevbu"/>
    <field name="s" type="svevbs"/>
 </union>
  <union id="svev">
    <field name="q" type="svevnq"/>
 <field name="d" type="svevnd"/>
    <field name="s" type="svevns"/>
    <field name="h" type="svevnh"/>
    <field name="b" type="svevnb"/>
  </union>
  <vector id="svep" type="uint8" count="256"/>
  <reg name="z0" bitsize="2048" regnum="34" type="svev"/>
  <...>
  <reg name="p0" bitsize="256" regnum="68" type="svep"/>
  <...>
</feature>
```
256 bytes is the maximum vector length for the simulated system. So it sends that, even though the program starts at less than that. When we change to that length, the types work again.
</pre>
<img width="1" height="1" alt="" src="http://email.email.llvm.org/o/eJysWFFv2zgM_jXKC1HDlhMnechD16SHAd1wt27dsJdCthlbN1lyJdld-usPktM2cdylMM4YsFQxP34fRTKimDG8kIgrMvtAZusJa2yp9GrNWp7f1jz7hdZOUpXvVt8MlwXYEgF_s6oWCJnKEbZaVVBaWxsSXxJ6Teh1wW3ZpEGmKkKvhWif_7uotfoXM0voNTemQUPo9WI-nUeExn4hU1WF0l7M5nQZzZYJnTFgMgfdSPnsvNaq0KyCxtN5wKq5YExnZTIl9Mq_YXc1GtgqDbd3G0LnBkgS_iRJCBoLbixqYBpBSbGDxmAOjyVKb9liZpUGgbKwpZOZWbGDitmsROPfMPwJQW0P_NiSWfhn8-kbcMktZ0LswKC0AQkvSXj5veRZCdyAVZC60NWYWcwD-I5QKLfKQCjrMbVqUoFurWK_EEyj8cWp6WhAU_uIOK9emlS68j4ZFEq5L7gsXCTSxjr9PU3cAANTY8aZgIwZ9DSTcP8vvLwg8QaiObiHb4HQRa0zKwhd_P3l_vZuc3-7-Xp_d-M80FlC6BJIvCbxGi4i_8f8gwOMr4IgIPHGfaYLIfLUffkSfo0sh7aAJ-cR3CeHEP4Oj58FEBrDXV_AgtDLBYnXyRTSnUUTeJCn8BDkhQEcPw7ws3pl4vawSwKXL09hAMeUJbz5OKhbizWoFnUvzFnJZNHF9iAUPraUemtmKmiVYJYLJHThJYBDvNvcf9n8dUvo4uPnj1_vfxK6_N8iSsMj9ieRleoRYroPL50lb8T3kEwHFq_dzv85Vl9L7MWdGx96j__wDNLLx5ub9QewujG2K8CWicZXIEnCtnBF7cPP5K6rTYMWuHx19OOTz1Wj4BF92TPxyHYG2L7Sas2lfXndPFfOa307G-__uQH9-HTjXe0L3Jd-jibTPO2aRAXM98JjISS-2iKzrqYlq9BVDaVKF0Ehm6DI02DfxQLTIqH0ObokvtqnFs87G9Ni-9AQSj3Bbq3h0kZ04RYz1UjbrUaJA6LXZ7DMMdZ7oIaR8m0PCRHvc9_UenAuyc4zywdUujY_BupU5EgkMyTS_RadiPQOzuMNiPRM_gD1BtKpxnNAbyCVQxpLJrb9rPB5ch5uKFuTkVgD2XoOahgpHWDVT3v_E3eeVHpK6j1IjeRKHgHJh4PS9-9sOYr8oGP0SL80gwPkQTszYGdOGBF67Um9Bm6AY36O4_bUl28N5zgOaMtHastNPwN60t7QZkZoM9u-r3cIMyOFmbOb9oaycoSycuSulSPFlWPFpSPKJh1JMh2XWucYPpx66rrBnxIrHzDKx8mS5h125YBd-Q67dMAufc9enzbbelzX1lgc8HkKnUnKrTvI7Y3CqcfRWMim2p8Ipqe8T5APjsInfuoBP57ckZtkceKmfttNF6j9WXK_dHDOfDm2-6GzRKjYb141VW9CceNON1tWjWAWczA7Y7EK4FYBt26Ezc1-zLwCbP2ErJqiPBrCjWXaGmAWBBr_uvQ2AXx3M_Uj7ichd9L2g3Ln_XhSf1T6F7CCcRlM8lWcL-Mlm-Aqmi_pbElnUTQpV0kUJSHOcJslYcyy-XaRRNtovlxkdDrd0njCVzSkSRTSKJrSaBYF8zxLk3k4S5At8xlOyTTEinERCNFWgdLFxF85rGg8pTSeCJaiMP4WhNJuvKJktp7olb-5SJvCkGkouLHmFcFyK3DlR5RcoZufLGRKa_T3Bqyuxe545PHXACZjwo8fL1OHG7MvL_3xv7uzWE4aLVbjb1X2otoV_S8AAP__47cpUg">