<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/217834>217834</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            [X86] allow vector integer division without prefer-vector-width=512 under strictfp
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            backend:X86,
            missed-optimization
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          Andarwinux
      </td>
    </tr>
</table>

<pre>
    https://godbolt.org/z/Mhscjf1d9

```c
#include <stdint.h>
#include <limits.h>

typedef uint32_t u32 [[clang::ext_vector_type(4)]];
typedef int32_t s32 [[clang::ext_vector_type(4)]];
typedef double f64 [[clang::ext_vector_type(4)]];
typedef _Bool i1 [[clang::ext_vector_type(4)]];

u32 foo(u32 a,u32 b){
    f64 x = __builtin_convertvector(a ,f64);
    f64 y = __builtin_convertvector(__builtin_elementwise_max(b,(u32)1),f64);
    return __builtin_convertvector(x /y, u32);
}

s32 bar(s32 a,s32 b){
    f64 x = __builtin_convertvector(a ,f64);
    i1 mask = ((a == INT32_MIN) & (b == -1)) || b == 0;
    b = mask ? 1 : b;
    f64 y = __builtin_convertvector(b,f64);
    return __builtin_convertvector(x /y, s32);
}
```

To comply with strictfp, we cannot introduce floating-point exceptions. Luckily, for integer division use cases, exceptions are only triggered when division by zero and overflow in signed cases. We should be able to implement vectorization by safeguarding such scenarios.

avx2
```asm
.LCPI0_0:
        .quad 0x4330000000000000
.LCPI0_2:
        .quad 0x41e0000000000000
.LCPI0_1:
        .long   1
foo:
        vpmovzxdq ymm0, xmm0
        vpbroadcastq    ymm2, qword ptr [rip + .LCPI0_0]
 vpor    ymm0, ymm0, ymm2
        vsubpd  ymm0, ymm0, ymm2
 vpbroadcastd    xmm3, dword ptr [rip + .LCPI0_1]
        vpmaxud xmm1, xmm1, xmm3
        vpmovzxdq       ymm1, xmm1
        vpor    ymm1, ymm1, ymm2
 vsubpd  ymm1, ymm1, ymm2
        vdivpd  ymm0, ymm0, ymm1
 vcvttpd2dq      xmm1, ymm0
        vpsrad  xmm2, xmm1, 31
 vbroadcastsd    ymm3, qword ptr [rip + .LCPI0_2]
        vsubpd  ymm0, ymm0, ymm3
        vcvttpd2dq      xmm0, ymm0
        vandpd  xmm0, xmm0, xmm2
 vorpd   xmm0, xmm1, xmm0
        vzeroupper
 ret

.LCPI1_0:
        .long   2147483648
.LCPI1_1:
        .quad 0x3ff0000000000000
bar:
        vcvtdq2pd       ymm2, xmm0
 vpbroadcastd    xmm3, dword ptr [rip + .LCPI1_0]
        vpcmpeqd xmm0, xmm0, xmm3
        vpcmpeqd        xmm3, xmm3, xmm3
        vpcmpeqd xmm3, xmm1, xmm3
        vpand   xmm0, xmm0, xmm3
        vpxor xmm3, xmm3, xmm3
        vpcmpeqd        xmm3, xmm1, xmm3
        vpor xmm0, xmm3, xmm0
        vpmovsxdq       ymm0, xmm0
        vcvtdq2pd ymm1, xmm1
        vbroadcastsd    ymm3, qword ptr [rip + .LCPI1_1]
 vblendvpd       ymm0, ymm1, ymm3, ymm0
        vdivpd  ymm0, ymm2, ymm0
 vcvttpd2dq      xmm0, ymm0
        vzeroupper
        ret
```
avx512 (prefer-vector-width=256)
```asm
.LCPI0_0:
        .long   1
foo:
 vcvtudq2pd      ymm0, xmm0
        vpmaxud xmm1, xmm1, dword ptr [rip + .LCPI0_0]{1to4}
        vcvtudq2pd      ymm1, xmm1
        vdivpd  ymm0, ymm0, ymm1
        vcvttpd2udq     xmm0, ymm0
        vzeroupper
 ret

.LCPI1_0:
        .long   2147483648
bar:
        vcvtdq2pd ymm2, xmm0
        vpcmpeqd        xmm3, xmm3, xmm3
        vpcmpeqd k1, xmm1, xmm3
        vpcmpeqd        k0 {k1}, xmm0, dword ptr [rip + .LCPI1_0]{1to4}
        vptestnmd       k1, xmm1, xmm1
        korw    k1, k1, k0
        vcvtdq2pd       ymm0, xmm1
        vdivpd  ymm0, ymm2, ymm0
        vmovapd ymm0 {k1}, ymm2
        vcvttpd2dq      xmm0, ymm0
 vzeroupper
        ret
```
</pre>
<img width="1" height="1" alt="" src="http://email.email.llvm.org/o/eJysWFGTojgQ_jXxpWuskKjggw-OnlVbtbt1D1t192YFEjQ7kDBJQJxffxVARWXG2d2jrGGku790f83XAZm1cqeEWKDpM5quR6x0e20WS8WZOUhV1qNY8-Ni71xhEV0iskFks9M81pkba7NDZPOGyObb3iY_04DPEV76zwy3n8R_IVSqJCu5AERX1nGp3HiP6F93tkzm0tmzDS_dsRBcpFBK5SjZOigpgSbT5yRjauczoktRu20lEqfN1gcgEk0QmaPp2n_ocw_nBGP_DIbrMs4EpLPJn6Bsn7XOQAa_g4Hw0lORao1I5P9jiKz8OfaOoXcBgCbDGhBdw3YblzJzUm0TrSphXIuPSMQAkVU6a1ag_cDjg8CLRWQiF8odpBXbnNWIRDEiqzYzROaBh75fwwhXGvXBAjUgsjkisoIWpys9XLcE-CbGzDvajgD7_xEgA8iZfWlCEYlaN7r2X798_0HJ9tuX74jMAZGZt8cn41Nb7BxQuELhCs4GfMFurp3gNxAAokuIf438-M8ItfeEniTbkvtDQ6LzIjvCQbo9WGdk4tLCxx4EJEwp7bycjOZlIiDNNHNS7Z4KLZUDUSeicFIrO4avZfIis2bVVBsfI3bCAJeVtFIrKK3Hs8J6j0sgMCNAq-wIzsjdThjB4bAX6hIYH-FNGA1McdCVMGmmDyAVNAONt5hj-EeA3esy4xALYF62ToPMi_aWhZYb-cZcB2lZKnYlM1yqHdgy2YNNhGJGajtuqWFVTfqEMZsjvBx_Xf39BW-xV3DbDn-MX0vGAdcTSnH_uASQdwIC8U5AcBOQabUDgADhpR8HV8aqyHX1VvNXOOY59gTX_tx3iI1mPGHWvfrvxzwn3u31oA2Hwhk_nIwsAJFnOJc49TcMVIU2XUwD3TuT_hK2jAv-vlsvBe796zyn3s4_SCHoUriUyeqS-9CgK_J0poNstMex7953O9cVdIkGVwlfChq0n2C4rN6pu1mtSirnCk5O6dQXmOsOWcN4Yyb92mgLcubO8i5n-qh_5Ia89_tzRd59ungoXaZ4wS_m3rklTxtv7l8Phu5Lr-yyKITxF41wrfSaCoI7kXUSIMEknER0Nokurrdq6eRF0_RWXn4ruRZPUjn-Spp0-9o4pfrrN25w1s65uUleiFc-RBcd8oMz-fTs9oF7zz4sCD87B5t17VZr8-k171McXrqFxDeQ-Fav9kqvgzPs3Kf3BP3LIgnOE6aKM6F41b8J8I3o6ZAM7sVP-m6fVdOVDLqjU0Nvv2ZVPQ2Ifw4pjEiFeWp3taeD5G6P6JpMZ363_-yeNbij-IzLnhze3VCGR_FH07wRRfgcOD1pn0X6nb1Zc7C_DyZtD81zXnakf4rz3xk9H0yS2xnyWDwfau3l4-3uGvQFAwqfXwLPcU_sD8fVYGcKJ6xT-Qn8LpE-8S_aHC5O3d9hBd_dWw_6TIYamOuKtVxfV3y7QT_Q4GfEN-ILyud0zkZiEYRRSOYRnkWj_SKKGEnCKaaYp7MkpiEl8xBPkihlQZAGYiQXBJMZjkiAw0mAozEmPMFslkwJCcQsImiCRc5kNs6yKvev2iNpbSkWJAgjOhllLBaZbV7bCYlZ8iIUR3T5bzRDhDRvXySX1gr-pAsn8-4J19um65FZeNCnuNxZNMGZtM5elnHSZc3vAR5rugaW-QfrdqTcP7771wNdOhiePH4slYoLc36DGJUmu_05Qbp9GY8TnSOy8Wl0p6fC6J8icYhsmtItIpuu-mpB_gsAAP__iVTRWw">