<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/209334>209334</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            [AArch64][X86] llvm.smul.fix.sat with scale = eltbits-1 should select vector ops, scalarizes to 100+ instructions instead
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          guyfischman
      </td>
    </tr>
</table>

<pre>
    ```
define <8 x i16> @f(<8 x i16> %a, <8 x i16> %b) {
  %r = call <8 x i16> @llvm.smul.fix.sat.v8i16(<8 x i16> %a, <8 x i16> %b, i32 15)
  ret <8 x i16> %r
}
declare <8 x i16> @llvm.smul.fix.sat.v8i16(<8 x i16>, <8 x i16>, i32)
```

On trunk, `llc -mtriple=aarch64` (https://godbolt.org/z/bvW47cxh7) scalarizes this to a 100 instruction per-lane expansion, even though `smul.fix.sat(a, b, 15)` is exactly `sqdmulh v0.8h, v0.8h, v1.8h`.
Likewise, on x86 with `-mtriple=x86_64  -mattr=+avx2` (https://godbolt.org/z/sPz59WYz9), LLVM scalarizes the vector instead of expanding it to vector instructions.

</pre>
<img width="1" height="1" alt="" src="http://email.email.llvm.org/o/eJyUk0GTozYQhX9Nc-kyJSQQcOCAx_FpUskpm5xSAgQoK5AjCZbxr08Je2q94xxmq1xlIZ7o9z51C-fUMEtZQXaE7BSJxY_GVsPy1ivXjpOYo8Z0bxVwcv-RupO9miUCeylwQ5VwYL8gpKQHWnzYpJkA-vJRSrMGaImQH4HUGJ4tAjthK7R-_qzW6xS7adFxr7bYCR-vRXj7M8VeUDGKSQa03Eta6Z91FkgN-WlP2Gph_yfiJ7082bg7uJV_ZAmk_m1Gb5f5636IE61bPEzeqouWwE5C2HbkKXCCQIvR-4sDVgM9Az0PpmuM9rGxA9DzFei5Wb-kebuNeeDrWqGFVVfp0I_KoTcoMCEE1ey8XVqvzIwXaQ9azBLldhGzU2YOPuQqZ_SjWYYxeHpMDLTYMe9Ub0Q5QeVQbqL1-m3X_9tNix5xJXExBt33RRIWnMRA6lf1VX5TToZ9M-NWcPym_F7wAcBW8L95iniYhPcW2AnoUawb_SQR9_s1K7_8dS2DUfqCr69__PojGYmrbL2xOxYpOjT9DUan5gGVD9weFHdwLiSIuop1JStFJKskL1hZsDLn0VhlOZeZFJKUXVkWMmNJXhR9WmYtIQ0VWaQqSignecIoIzzhcVrwJhU9b0WZctFTSImchNLx3nLGDpFybpEVJSVjaaRFI7V7n1pbBdWhWQYXmlQ5776f88rrfb7r-tZK2Qmy458Fh-yETw19u4IASO4zKbVvlHeHBN1oFt2hk1q2_p2IubhA9RGoCT0G9PgDrXe40WJ19eHOlB-XJm7NBPQc_Nz_Dhdr_pGtB3reozug53v6taL_BQAA__8GcGi_">