<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/202190>202190</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            [RISC-V][lld] RISC-V shared SET* preemptible/undefined wrong success
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          XiaobingHou1219
      </td>
    </tr>
</table>

<pre>
    I ran into this while reducing a RISC-V linker testcase. The reproducer is small, and I have been seeing the same result consistently across three reruns.

### Summary
ld.lld 22.1.0 links the default-visible shared objects successfully, exports `ext` in `.dynsym`, emits no dynamic relocations, and writes the local `ext` address bits into `.rodata` SET6/SET8/SET16/SET32 fields. It also links the strong-undefined shared objects successfully, keeps `ext` as `UND` in `.dynsym`, emits no dynamic relocations, and writes zero bytes to all SET* fields. Hidden `ext` and `-Bsymbolic` controls also link, showing the relocation encodings are valid when the symbol is non-preemptible.

### Expected behavior
Link RISC-V shared objects containing public psABI `R_RISCV_SET6`, `R_RISCV_SET8`, `R_RISCV_SET16`, and `R_RISCV_SET32` relocations in SHF_ALLOC `.rodata` against either a default-visible function `ext` defined in the same DSO or a strong undefined symbol `ext`. The psABI defines these SET* relocations as static `S + A` local-label assignment relocations, so a shared link must not silently materialize a preemptible local definition, and it must reject an undefined strong symbol because there is no dynamic SET* relocation to defer the value.

### Environment
- linker route: GNU as 2.45 and LLVM MC 22 inputs; current ld.lld 22.1.0; GNU ld.bfd 2.45 observed with the same wrong-success behavior; hidden-symbol and `-Bsymbolic` controls are exercised
- march: rv32imac and rv64imac
- mabi: ilp32 and lp64
- first failing stage: link
- local stability check: True

### Reduced testcase
These are the reduced input files from the minimized reproducer I used locally:

#### `default.s`
```asm
  .text
  .globl ext
  .type ext,@function
ext:
  ret

  .section .rodata,"a",@progbits
  .globl set6
set6:
  .byte 0
  .reloc set6, R_RISCV_SET6, ext
  .globl set8
set8:
  .byte 0
  .reloc set8, R_RISCV_SET8, ext
  .globl set16
set16:
  .2byte 0
  .reloc set16, R_RISCV_SET16, ext
  .globl set32
set32:
  .4byte 0
 .reloc set32, R_RISCV_SET32, ext
```

#### `hidden.s`
```asm
 .text
  .globl ext
  .hidden ext
  .type ext,@function
ext:
 ret

  .section .rodata,"a",@progbits
  .globl set6
set6:
 .byte 0
  .reloc set6, R_RISCV_SET6, ext
  .globl set8
set8:
 .byte 0
  .reloc set8, R_RISCV_SET8, ext
  .globl set16
set16:
 .2byte 0
  .reloc set16, R_RISCV_SET16, ext
  .globl set32
set32:
  .4byte 0
  .reloc set32, R_RISCV_SET32, ext
```

#### `undef.s`
```asm
  .text
  .globl local_func
  .type local_func,@function
local_func:
  ret

 .section .rodata,"a",@progbits
  .globl set6
set6:
  .byte 0
 .reloc set6, R_RISCV_SET6, ext
  .globl set8
set8:
  .byte 0
 .reloc set8, R_RISCV_SET8, ext
  .globl set16
set16:
  .2byte 0
 .reloc set16, R_RISCV_SET16, ext
  .globl set32
set32:
  .4byte 0
  .reloc set32, R_RISCV_SET32, ext
```

### Reproduction notes
- This packaged root does not have a single canonical `run.ps1` wrapper.
- Use the reduced inputs under `case/` and follow the commands documented in `case/README.md`.
- Stable witness outputs, when present, are preserved under `verify/run1..run3/`.

### What I checked
- Reduced inputs are preserved under case/.
- Stable witness outputs are preserved under verify/run1..run3/.
- The strict recheck says stable normalized run signatures across three runs: True.
- Tracker guidance link: https://llvm.org/docs/HowToSubmitABug.html
- evidence summary: 3 clean reproductions under hunt/verify/riscv_shared_undefined_preemptible_set_wrong_success/run1..run3` show stable GNU-as and LLVM-MC assembly success, stable input `R_RISCV_SET6/8/16/32` relocations, stable ld.lld wrong-success outputs for RV32/RV64 default-visible and undefined-strong shared links, and stable hidden/`-Bsymbolic` control success. Across the 96-link verification batch, ld.lld has 12 `wrong_success_default_preemptible`, 12 `wrong_success_undefined_strong`, and 24 `allowed_nonpreemptible_control` results. Representative run1 RV64 GNU-as undefined output has `.rodata` bytes `00000000 00000000`, no dynamic relocations, and `UND ext`; representative run1 RV64 GNU-as default-visible output has `.rodata` bytes `14545413 54130000`, no dynamic relocations, and global default `ext`. Local records already had ADD/SUB shared-preemptible roots, but no SET* single-symbol/undefined-strong root. Web searches over LLVM GitHub issues, Sourceware Bugzilla/list archives, and broader queries for `R_RISCV_SET6`, `R_RISCV_SET8`, `R_RISCV_SET32`, `undefined`, `shared`, and `recompile with -fPIC` found psABI/source/review references but no direct current issue report for SET* wrong-success/no-relocation output.

### Notes
Current RISC-V psABI relocation table defines `R_RISCV_SET6/8/16/32` as static `S + A`; LLVM review D39323 shows lld's RISC-V `usesOnlyLowPageBits` path historically included SET* with ADD/SUB to avoid dynamic relocations, while current local lld 22.1.0 still accepts these shared-link cases.

Root key: `lld.riscv.shared_preemptible_set_wrong_success`
Case id: `20260605-lld-riscv-shared-preemptible-set-wrong-success`

</pre>
<img width="1" height="1" alt="" src="http://email.email.llvm.org/o/eJzUWV1v27jS_jXKzcCCTTmOc5ELx6m3AdLuIkm7751BkWOLW4r0S1J23V9_MKRky27SLBabA5wgSCyKHM7HM5_m3qu1QbzJLm-zy7sL3oTKupv_U9yWyqw_2mbERtcXpZX7m3tw3IAywUKolIddpTSCQ9kIZdbA4fH-aT74ClqZb-ggoA-Ce8zhuaJtG2dlI9CB8uBrrnXG5sCNhHuo-BahRDTgEYlWqBA8r-mYb3QAYY1XPqAJeg9cOOs9hMohbXCN8Xk2vMuGs_YvK9IvPDV1zd0-LWuZay2BsXyUDyOTPt4jccUbHQZb5VWpEXzFHUqw5V8oggffCIHerxqt98Qxft9YFzxkkyF-D9lkCMrQQy73xu_rbDKMu2oVPBgLcm94rQQ41FbwoKzxndw7pwImHuid7pHkUjr0HkqiEjVONzgreeD0_unD8yRji6cPz9P0b9Q-FgxWCrX0OdwH4NrbnqQ-OGvWg8ZIXCmD8i1RvyFu-oLy-PDl892_IPUPdBbKfVSABa41yZSx2YH9j0pKNP3bjaSnwa3f16XVStCisCY4q_1RVLrHV3bXwejIAqARViqz9sAdwpZrJWFXoUnKiVQJnMaawcYh1ptAgHgFWx--b1AElFBixbfKurThQZlvnSOcqZd45coQY5um1ErAxs9u70moxyUd-bqMdk26PF2dvrg66ja3uum9Khipp6d_MtjTx8Vy9vDw-_wMTnzNlfEBUIUKHfCffGLVGBFVeDRHhyFljt569_Q7WDqfkAY9pCXtHo6noJDkT3siRD12MOhzzj34wIMSdP4JMnYLM2Ihes1A8xI1pEBWownnoPOWGEqmIIBA3fgAxgbwSqeIUvOATnGtfiBw6Nm-dczIoSKKnbJVSGQckm2Bm76sSfhW5BIFbzySdA4TvA7u8ZOs5AsSVxQ9q4jQ5lX4ma1yNgqcXg26uOtsEzArZvDb5y-kOpaPLyPPDw9fP8GnOTAGymya4LPiFkTjHCntJDrSCzqtZV6uZKJgS49uixJ2KlRHk-9iSGkjx9EXiluoogMPWjW84b0OAb-jE8qj7OSpuRMVCeK2BVM1F5GI207G9HDcVSrapPSmYHGH3kzG3duVcj7AiitNbucDX0fVxEDRqS2a2AdeKq3CHkSF4httenYNvqz8R8p5KA8pLr1_jvglUVLcSXuiqmGlNHpYOVvHl7UyqlY_UPbz4j00njBK_Oh9VsxevJzuzybD1kNzTxEg7ZgM0y_3dVoByAO5W_ew1rbU0F8J-w3GBTbPxsPOy9NrWu54AHAY-uwA5B5TSOjiCJtnjPGMsURs4-ya0tfZ7R7DJC3FT8cLckoGMDw8RqdI29kcTgJkzMLnYnkM0wPh6d8hPD0jPH2V8OjI8uiEZ_Ya7dE516PX2S7YgXrB-tTHJ9SPxAt2RjwtHIgfkPArACX3_DV-3oJPovHPEPXegHovPL0fnP6raPq34RTT3z-IRjHaLQknpxDqrb-ApN7b10PU-0ao9wpQ7xif_jcABY9tSoy2Mzag71L1M7WdGy6-8TWlTmsDSIs-FnOxh-TglVlrBMGNNaptqlxj8o0fUcWxc3yzQZd3FL_4F7K1j8Wco6Mxu7NF13-srNZ2F08IW9fcSA_SiobKsFQLH888fpjdffqQ15LK3e6-p8CprNypYKhesk2IhRibp0Zk49BTRUdVpsP0GIuuA0NbdGq1z9jCNWaU564xReLvlTrxz4oHuE9FzbG0ejwV96W7Wine4PzFoy_zmB-tGFtRJah8joyB5_tY49MNxro6luISXGOAynoeGof-rPFvjO-qtCNpxwXVwOtGSW4EpkKvmEEVwoa2k67YQuttnVu3zthCWuEztvhod8_2qSlrFWa3zTqvQq07orhVEomYb8cJxQwKEBq5OZRvqVFJ4lcNWXBx1ILyYrtMHcjy0CYse23G0mNYxkp62VbSp8qbDGNL22not89fBtwfavrBpzm1P1iXeg-H8_NudypAz5tMtphmbBHHBj-1ir3DbVtwWuV3tl9ZB49fybkXj18n45-6RmLwIO-ga4uOndhhJtBelsqJBOcXG4VOuhxmHRQQrieD2NZFfau2jyp5EBWRbwWouIcRIy2cqHnZstw3RttSv7T7aLwkTK_7ZmPazik8oFwaa_rmbdlPavaNDj6PUS46Ow9qG-E8gqjF1rrHfjKpO4pw2ran8Uk2GXY_0H1oGfv1JCbNciA15NSxuTdYOrfv24yNxpfjy_GoAPrztxmj1JO6brquPzR4iL2aQ2Gd9MC1Qy73UHEJs7u7jC2evty2AOtPcGKmiNTLhjr_ru9OuaLtUDO2-AmrdC6HP7EEj9SMoge7RZc66d9U-NiUoLxvMBJ_so0TuKOIeNusfyitOcUa5QPQYbXFg4Sls5xCxf836BQmT_rnY6DowO3yQYbjUlLI6aSIVFhvVAroFQxWf9zPyXIr2xiZ5jIZW_goEcUi3CrcgcMVOgqFvtOkVA5FOEwRojIIR9aFKFSr6ZP4kbGFsYPe0CPh6JUE9vlYAMzbW9rxWpoe9YcnMYp046Q3I94rYyXyhGjgVui74rpgRQzAHrSWGbvyHQukcI_-d6P3D3b3B1_jLRWUkyFseKigUj5Yp2I_D8oI3UiUB52Q4o-wDRb41ir5mmOkafthXBMdoTfP9kFpDVwI3IRulNZ6QoyOlM5Px-SPVD59w5jOsslQa5nHTJW3merX-akr3ubcIyjZEmFDNhlOhpcDreUgUhv87I4Dj2FwioiO2oW8KeR1cc0v8GZ0NR1Oi8n11fSiuhFX45Es-bVYDcfsWkp-fVWMh4KVUyG5GBcX6qa9-2rELiejaX4l8fKSlsorWY4Klo2HWHOl8y75X0Sw0rHR9fAiThF99zWIu6Fdg7JZ-2w8JBf2x3NBBR2_MEkgyC7vsstbAsbl3dnkt7V0P7n0okzyii6nXTRO35yWKWsVqqbMha3bmqX9N9g4-xcKKjK66LNoxdjesP8EAAD__-UxJPM">