<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/163478>163478</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            [Github] False positive(ish) on undef checker
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            new issue
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          boomanaiden154
      </td>
    </tr>
</table>

<pre>
    For the following patch (https://github.com/llvm/llvm-project/pull/163319)
```patch
>From bd4bc1ef007e50e5838aed9ae93a8b4eeb172eda Mon Sep 17 00:00:00 2001
From: Mircea Trofin <mtrofin@google.com>
Date: Mon, 13 Oct 2025 20:50:10 -0700
Subject: [PATCH] [sroa][profcheck] Vector selects have "unknown" branch
 weights

---
 llvm/lib/Transforms/Scalar/SROA.cpp      |  4 +++-
 llvm/test/Transforms/SROA/slice-width.ll | 19 ++++++++++++++++---
 llvm/utils/profcheck-xfail.txt           |  8 --------
 3 files changed, 19 insertions(+), 12 deletions(-)

diff --git a/llvm/lib/Transforms/Scalar/SROA.cpp b/llvm/lib/Transforms/Scalar/SROA.cpp
index d2f09e9f3c639..578fec772603f 100644
--- a/llvm/lib/Transforms/Scalar/SROA.cpp
+++ b/llvm/lib/Transforms/Scalar/SROA.cpp
@@ -2667,7 +2667,9 @@ static Value *insertVector(IRBuilderTy &IRB, Value *Old, Value *V,
   for (unsigned i = 0; i != cast<FixedVectorType>(VecTy)->getNumElements(); ++i)
 Mask2.push_back(IRB.getInt1(i >= BeginIndex && i < EndIndex));
 
-  V = IRB.CreateSelect(ConstantVector::get(Mask2), V, Old, Name + "blend");
+ // No profiling support for vector selects.
+  V = IRB.CreateSelectWithUnknownProfile(ConstantVector::get(Mask2), V, Old,
+ DEBUG_TYPE, Name + "blend");
 
 LLVM_DEBUG(dbgs() << "    blend: " << *V << "\n");
   return V;
diff --git a/llvm/test/Transforms/SROA/slice-width.ll b/llvm/test/Transforms/SROA/slice-width.ll
index eabb6978c9125..3b77e49e78358 100644
--- a/llvm/test/Transforms/SROA/slice-width.ll
+++ b/llvm/test/Transforms/SROA/slice-width.ll
@@ -1,4 +1,4 @@
-; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals
 ; RUN: opt < %s -passes='sroa<preserve-cfg>' -S | FileCheck %s --check-prefixes=CHECK,CHECK-PRESERVE-CFG
 ; RUN: opt < %s -passes='sroa<modify-cfg>' -S | FileCheck %s --check-prefixes=CHECK,CHECK-MODIFY-CFG
 target datalayout = "e-p:64:64:64-p1:16:16:16-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:64:64-f80:128-v64:64:64-v128:128:128-a0:0:64-n8:16:32:64"
@@ -8,6 +8,10 @@ declare void @llvm.memset.p0.i32(ptr nocapture, i8, i32, i1) nounwind
 declare void @llvm.memset.p0.i64(ptr nocapture, i8, i64, i1) nounwind
 
 ; This tests that allocas are not split into slices that are not byte width multiple
+;.
+; CHECK: @foo_copy_source = external constant %union.Foo
+; CHECK: @i64_sink = global i64 0
+;.
 define void @no_split_on_non_byte_width(i32) {
 ; CHECK-LABEL: @no_split_on_non_byte_width(
 ; CHECK-NEXT:    [[ARG_SROA_0:%.*]] = alloca i8, align 8
@@ -92,12 +96,12 @@ declare i32 @memcpy_vec3float_helper(ptr)
 
 ; PR18726: Check that SROA does not rewrite a 12-byte memcpy into a 16-byte
 ; vector store, hence accidentally putting gibberish onto the stack.
-define i32 @memcpy_vec3float_widening(ptr %x) {
+define i32 @memcpy_vec3float_widening(ptr %x) !prof !0 {
 ; CHECK-LABEL: @memcpy_vec3float_widening(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT: [[TMP1_SROA_0_0_COPYLOAD:%.*]] = load <3 x float>, ptr [[X:%.*]], align 4
 ; CHECK-NEXT:    [[TMP1_SROA_0_0_VEC_EXPAND:%.*]] = shufflevector <3 x float> [[TMP1_SROA_0_0_COPYLOAD]], <3 x float> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 poison>
-; CHECK-NEXT:    [[TMP1_SROA_0_0_VECBLEND:%.*]] = select <4 x i1> <i1 true, i1 true, i1 true, i1 false>, <4 x float> [[TMP1_SROA_0_0_VEC_EXPAND]], <4 x float> undef
+; CHECK-NEXT: [[TMP1_SROA_0_0_VECBLEND:%.*]] = select <4 x i1> <i1 true, i1 true, i1 true, i1 false>, <4 x float> [[TMP1_SROA_0_0_VEC_EXPAND]], <4 x float> undef, !prof [[PROF1:![0-9]+]]
 ; CHECK-NEXT:    [[TMP2:%.*]] = alloca [[S_VEC3FLOAT:%.*]], align 4
 ; CHECK-NEXT: [[TMP1_SROA_0_0_VEC_EXTRACT:%.*]] = shufflevector <4 x float> [[TMP1_SROA_0_0_VECBLEND]], <4 x float> poison, <3 x i32> <i32 0, i32 1, i32 2>
 ; CHECK-NEXT:    store <3 x float> [[TMP1_SROA_0_0_VEC_EXTRACT]], ptr [[TMP2]], align 4
@@ -158,6 +162,15 @@ define i1 @presplit_overlarge_load() {
   %L2 = load i1, ptr %A
   ret i1 %L2
 }
+!0 = !{!"function_entry_count", i32 10}
+
+;.
+; CHECK: attributes #[[ATTR0:[0-9]+]] = { nocallback nofree nounwind willreturn memory(argmem: readwrite) }
+; CHECK: attributes #[[ATTR1:[0-9]+]] = { nocallback nofree nounwind willreturn memory(argmem: write) }
+;.
+; CHECK: [[META0:![0-9]+]] = !{!"function_entry_count", i32 10}
+; CHECK: [[PROF1]] = !{!"unknown", !"sroa"}
+;.
 ;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
 ; CHECK-MODIFY-CFG: {{.*}}
 ; CHECK-PRESERVE-CFG: {{.*}}
diff --git a/llvm/utils/profcheck-xfail.txt b/llvm/utils/profcheck-xfail.txt
index a5c5426870a7d..3f8be5e240762 100644
--- a/llvm/utils/profcheck-xfail.txt
+++ b/llvm/utils/profcheck-xfail.txt
@@ -1310,14 +1310,6 @@ Transforms/SimpleLoopUnswitch/pr60736.ll
 Transforms/SimpleLoopUnswitch/trivial-unswitch-freeze-individual-conditions.ll
 Transforms/SimpleLoopUnswitch/trivial-unswitch.ll
 Transforms/SimpleLoopUnswitch/trivial-unswitch-logical-and-or.ll
-Transforms/SROA/phi-gep.ll
-Transforms/SROA/scalable-vectors-with-known-vscale.ll
-Transforms/SROA/select-gep.ll
-Transforms/SROA/select-load.ll
-Transforms/SROA/slice-width.ll
-Transforms/SROA/vector-conversion.ll
-Transforms/SROA/vector-promotion-cannot-tree-structure-merge.ll
-Transforms/SROA/vector-promotion.ll
 Transforms/StackProtector/cross-dso-cfi-stack-chk-fail.ll
 Transforms/StructurizeCFG/AMDGPU/uniform-regions.ll
 Transforms/StructurizeCFG/hoist-zerocost.ll
```

The undef checker still flags it despite the `undef` being genrated by a pass specifically due to a load from uninitialized memory. The `undef` is also not new and has existed in the test previously.

This warning significantly reduces the signal to noise ratio of the check. For this case, a simple heuristic that counts `undef`s removed `undef`s added and only signals when more have been added than removed should suffice.
</pre>
<img width="1" height="1" alt="" src="http://email.email.llvm.org/o/eJzUWV1z4ryS_jXKTZcpW8YYLnIBBOZMbWaSyjDZ972iZLuNtSMklyWT8P76rZYNhBmSSebsXpxUQow-Wo_641G3LKyVG414zZIZS26uROsq01xnxmyFFrJAHSXDq8wU--ulacBVCKVRyjxJvYFauLwCxseVc7Vl8ZTxJePLjXRVmw1ys2V8qdTu8C-oG_M_mDvGl3WrFOPLaBTH0YTxCQunbBR2v14qC6fLxmwhK4ZZHmEZhikmISbjeCywmAicxGKcDRGzKOVYCPhiNHzDGqIUwpDF0_4DeBhGvTAWT-GLbHIUsGpMKTWweL51_pENw40xG4Uedrxg4fRGOPRTjGZ8DlEMd7kDHvIEOAlP6CMKIQjTMGTh9Fub-d3FU2DJ7H66mv-LJTf0bBsjWHLDklndmDKvMP9BPY-YO9OARYW5s1CJHQLjvNU_tHnSjHPIGqG9LuAJ5aZylvQUToMgoLaDamXG-HLVCG1L02wt48tvuVCioYeHu-kgr2vwPyydAwyB8Vn3-1KKQ-t-EfNwRya1SuYYPMnCVQOlvJRocpLyzt9z0K2TipY4KiR4LoVUA_fs4PTjAY8h6H9ofgylVGghr4TeYOEtMwGpLTZOGm0ZH_v1Jr6HQ4EKDx1B72nhtJBlCUGwkQ7ECyd9jyazj41n4VTqAp-h4GU4wUkZ56N4Mhgk6bjEPE35KIxLiMJwNBx2pv0oItrRQcl_gI4NQzYMIeCjUcr4PCXD9s8T6DutE07m8ChUSy467dTd-S_j488Ps1aqApvVHhgffX6YkfKPo-9Ucfb9kfE5mRKgNA3RR6s9CRUggcU3ELJ4Ro88om-5sI7F86V8xqJbcbWvkUKUjx8xX-0ZnwQsXmzQfW23C4Vb1K5zgwkJ6hQjO9PDF2F_8EHd2mqdifxHB36wQfdZu4jxMSFY0LIz3Ej92VuO8RHjIw9uDgtd-FbvYbQASSXDATx69CRv3qBw-M0HNuPjudHWCX1QWDxl8XSD1OPh9M5KaoFeV1_FllRF6HmmUBeM8-NyXTsxLXw1QBEkFdGxbevaNM5rdXfGLYN-1isQ_1u66nvHOvdeGv4J6H6Nm8Xs-6f16u_7xW83QnqD29vHL2s_ifFxkW1605GySd9EgwDQzSVq5fzUNX18MYwlc30mHaBB1zYaHruGy0H_fuLL_mDSMfxRZNloko7zScSTwSDO0hSHE0zHcTJ-Nfw_ssxFDviQgJ4IIsbn_pDoH3wzYaNo-nq3WpAZpvZAuN25lSFqEK0zG9TYCIcFZHs4sHxbF8LhmtCsPdvbQb3vMf_fCoXvq_l6-vDpG8kLgu5o2SiTCWW9x8UzePj-lXpN7aBzncRCUAtr0bL4hvHUn9fxvG7QYrPDIC83nm9SCL75M2kpFc5JdD-5X6dusJTPXsr8X4v5fzE-9_-D-4fFt8XD4yKYLz99FMXWFLLc__sYvtzdfF7-fUDgRLNBB4VwQom9aZ0nBsY5BjWLp6Ph6SOoI0p0RqePQFLLmP4COT49no-JOYun_UcgvTD_bTQMyrO-8my1cuzzKj4Odmftu4iPu46-W_gMr-vU48PK_RJEBCeXHjM-H5FL00MUHo61AnMlGoSdkQW1UdAMtri16AZ1OKAd8HHtGtAmF7VrGyRKk2P_SZ1zkBFxlTatfpK6IM3-Tihhe1UodV4SenCaVSUtkMdbcJVwIJQyubBAC2rjwNZKOpDaGfDxfRjWd2d7h-BDHratcrJWeIzCwSkeO8chsh2GpTHr3NT7tTVtk6N3E3x22GihIO_PCHLBVkujB0tjLsuRo-HaSv3DC-gCkrYL4RkAKLCU-qQ8bdZ-S2uj19roNW1g7TdAZzWZYAIsnR3U03n67XS2uO2XfVPA-bSvi79WNIvyTiqGZtOHT2siy3XoS5tkwPjUp_E3fhOd7nvLCSU3GsYvfG5C_hFx8rrJqH88dzsZ-6YtbvN6v95hHpfKCLeuUNXYdF7Spy0HpPcP0Tjl5OfQxb43L4GEwqD1Rm7wqZEOQUDEA2_xboXOLQREI996EHnIFJzpPLFCnSOIPKfizwml9lC3zlGCsZFZho20FRgSRcWgdSL_QZYLesu9tqknEif1pnd-xpPnk_EYn_3hdB5R_kP_w7cd4S2Jr_gBatfsyfQXuzsfWX25j3onWYfr-d3937d305uL_qKMKIjqY3gGD8Hz-Rz8frywv36ed_Ks4W989RzH42K-Xvx1P_16GYmt2rJU2Fv-J0hvb-wI6-dZtZG2K5RZPB_CsydIkhbPyaZhz5kQHR744aGf6Wvu4CNbnN0uXtugT2uPSKIDkAhc03Z8-9pjKZTF3jL9_Dc180LVL3VzNq_VBZY_0eKbfvSftznqOMSiF3T_cLeMPP6IJbMwmPjps17Ob52Zv0W53ahvBC9e3t5NVx-Om9c3u3qYzn-Rdzlq3qO-zoyvKu8sauJ3RY2Pk8va8xz-rnh-udcjuBMReQNc0OSxREiOGVU08udccjrcOh6PqIEy6O703WGjKOVcEwseKry0L9MYT275iSNldETDk-mxkvMyaaTff3pzqHmI-X3uGpFAHjHOy1bnVEesPYWvc9Nq50vDXpvhafpb6Y9wrpFZ69AC43GfFKxWDz4f-MWpOxTpzCd2SmUi_wHalA3iMZWDJ6lUX5RucWuaPeNj0Wy26C8nGxSFP7s77dx8AFL0_wTpIpyLqaKH8mWxmoavRf2_Y6Zfl-oI5rLg0xVqT0yMc19Ocf7zPiiSXtagqwotwqGK8plzq1uLBQhd-JRHSetA2vPCdAA3xmdfoij6BD1DZZ7AUcaupMZfEokXBRltKp2xdOYpJ73pQL4Ye1ZAXh59-XbjrXvW7F3DjjcYIsmTIR-N01CkxWAQl-MME-TDMB3xV28w3hZ88c7iN1MOFBRHxI5Rd1PRfRkdSOj8vkNua4W3xtTftX2SLq-88FGYxqPu5uMd410jd1KooO2bAgqifzCQupA7WbRCBbnRhfS3F38s9c_hKLORuVCB0EVgmk5OcOnap65ksMH6jRE2F0pkCoPupLPBk3RV4AMq2FEnvjXZJye_W6EbRGT_1qifL6gujupAkvJ32FgqQX87tm7M1pChglxobVzgGsTAuqbNqRwPtths3trjz2IuWo3qovvGuP6OfJk3xtqgsCbISxn4sinIqx-Bd-2LAjo48h-kmOfL6ZebT_ffKT60pEFBg5tXne3nyZWR1gX_YGNyY11_33d44da9EllV2OVy4IMOqSSUSkGpxMaCdFCgramuJA5ko7DL-0YhZOhrQ9THGzoBtbAWbI25LMkt1R6KFsGXn_6ILxuzhVZLLZ0USv6DRX_4DIiAz8QT0yrbkavGJ0_DlbCAz9LSelJ7RMS5RNs7aVqr9oPDpqSFJ9Fofz8uN9rj0U7tocGi7S5I0PcIRfi0kRahEU4aMKXv9OoYQPf6U1rIhfX5tADrQxMqbBtpncy7atwfY_blHiw0uDU7LM4bRVH0x4rRat-DsPBUoYYtZXIvLkH9UFcJfRRlK9OqAmxbljLHwVVxHReTeCKu8DpKR-FwnMbR8Kq6TtIwnaRhicM8SzDNeJpHIo0mo2E4STM-upLXPORJFEZJGEZJNBzEo8loOBTJJOKTpCwyNgxx27npbjswzeZKWtvidTSKh-n4SokMlfUvkDknC_lefyF_c9Vc-ze_WbuxbBjS0WlPYpx0yr95_uTfGNNJvqQKBWpjpZM7ZHwsbUXph9HnznnVNur6w6-dPTLbvXgm6Ltr_r8BAAD__15QLZM">