<table border="1" cellspacing="0" cellpadding="8">
<tr>
<th>Issue</th>
<td>
<a href=https://github.com/llvm/llvm-project/issues/162111>162111</a>
</td>
</tr>
<tr>
<th>Summary</th>
<td>
[SimplifyCFG] switch on umin can be converted to use default dest
</td>
</tr>
<tr>
<th>Labels</th>
<td>
llvm:optimizations,
missed-optimization
</td>
</tr>
<tr>
<th>Assignees</th>
<td>
</td>
</tr>
<tr>
<th>Reporter</th>
<td>
nikic
</td>
</tr>
</table>
<pre>
https://alive2.llvm.org/ce/z/_N6nfs
```llvm
define void @src(i32 %x) {
%min = call i32 @llvm.umin.i32(i32 %x, i32 3)
switch i32 %min, label %unreachable [
i32 0, label %case0
i32 1, label %case1
i32 2, label %case2
i32 3, label %case3
]
case0:
call void @a()
ret void
case1:
call void @b()
ret void
case2:
call void @c()
ret void
case3:
ret void
unreachable:
unreachable
}
define void @tgt(i32 %x) {
switch i32 %x, label %case3 [
i32 0, label %case0
i32 1, label %case1
i32 2, label %case2
]
case0:
call void @a()
ret void
case1:
call void @b()
ret void
case2:
call void @c()
ret void
case3:
ret void
unreachable:
unreachable
}
declare void @a()
declare void @b()
declare void @c()
```
The umin here maps "all the remaining cases" to 3 and then has an explicit case for 3. We could use the switch default instead.
(This inverse of this does seem like a reasonable backend lowering strategy though.)
</pre>
<img width="1" height="1" alt="" src="http://email.email.llvm.org/o/eJy8VcGOozgQ_ZriUmpkyoGEAwemI_a2lx1pjytjiuBtYyJsMt3z9SuTdHe6k9k9rNRSpMi8etjvvaKsvDcHx1xB_g3yfaKWMExz5cyT0Uk7dS_VEMLRg6yBGqBGWXNiSq09jek0H4AazUDNT6Dmr98L13sQNRTi_ItVIOqOe-MYT5PpEDbCzxpoZyQhUP4MVCJsv4GoMa5H4xDkHrWyFteazfqadBmNS42kD9THtUQClZHvf5igB7zAo3GxwKqWbVwvbmalB9Vaxig2bohrsfhQp5VncYVmN2h2hdINSleovEFlRCHfR5tEfd5L1mfKqvnVJQW0u-hCnDmswDsru89q31m3HLrP0f--k3xjfcSu_HyruH4matheZH5qgHAI9xvgY4DPt-Z9QXBfks091n-n83-y-WUy2qqZ7yj7jLS_RC4nxOsvH0T9fWCMHy0OPDOO6ugRiKK0MDDOPCrjjDtg1OGBCMOEEpXrIu5wUB6VQ34-WqNNWMuwn2aUKf7JqKfFdrh4Xt92aZyOe7XYgMb5wKpLzxqBdt8H49G4E8-eceoxxHU3sUfPPKI1T4wKZ1Z-cuuAaJV-YtehnX7wHE_pw6wCH14wDNNyGFKgMukq2ZWyVAlX2TYvt0VRlJQMldaFzDLBm6LjzS4nUfJ2WxZlsd11YifzxFQkKM-EKLJCbHJKZd_npMW23fRCCt3CRkR_7NucTYz3C1dZQVmWJWvb-nVkE61DVtbTMZjR_FTBTC7aCfQIRKPxnruHazBi-T6Zq0h8aJeDjyPW-ODfdwsm2PVK-MOMR2v6l8fmN8j3rz5P7pysVg7bmEV0NnAXI4yRvObQsQ_JMttPd8jBhGFpUz2NQM16_PPfw3Ge_mYdgJpVrgdqLopPFf0TAAD__-4D9kw">