<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/155452>155452</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            [SelectionDAG] Underflow leading to an assertion
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            new issue
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          Saldivarcher
      </td>
    </tr>
</table>

<pre>
    Found that this IR:
```llvm
; ModuleID = 'reduced.bc'
target triple = "amdgcn-amd-amdhsa"

define amdgpu_kernel void @my_kernel(i64 %foo, i32 %bar) {
entry:
  br label %loop

loop: ; preds = %entry, %loop
  %i = phi i64 [ 1, %entry ], [ 0, %loop ]
  %mul = mul i64 %foo, %i
  %add = add i64 %mul, 1
  %trunc = trunc i64 %add to i32
  %div = sdiv i32 %trunc, %bar
  %sext = sext i32 %div to i64
  %or = or i64 %add, %sext
  %inttoptr = inttoptr i64 %or to ptr
  %addrspacecast = addrspacecast ptr %inttoptr to ptr addrspace(1)
  %val = load double, ptr addrspace(1) %addrspacecast, align 8
  store double %val, ptr addrspace(1) null, align 8
  br label %loop
}
```
Leads to an assertion, and it's due to `ComputeNumSignBits` returning a 0.  This is the segment of code that causes the underflow:
```c++
  case ISD::ABS: {
    Known2 = computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1);
    Known = Known2.abs();
// setHighBits is where the assertion happens, the `-1` is what causes the underflow.
    Known.Zero.setHighBits(
 ComputeNumSignBits(Op.getOperand(0), DemandedElts, Depth + 1) - 1);
 break;
  }
```

https://godbolt.org/z/M6hq64dvE
</pre>
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