<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/155014>155014</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            risc-v backend miscompile of cttz-related optimization
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            bug,
            backend:RISC-V,
            miscompilation
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          regehr
      </td>
    </tr>
</table>

<pre>
    this function:
```
declare i7 @llvm.cttz.i7(i7, i1 immarg)

define i7 @f(i7 %0) {
  %2 = call i7 @llvm.cttz.i7(i7 %0, i1 false)
  %3 = icmp eq i7 %0, 0
  %4 = select i1 %3, i7 0, i7 %2
  ret i7 %4
}
```
is getting miscompiled by the RISCV64+B backend as:
```
f:
        ori     a0, a0, 128
        ctz     a0, a0
        andi    a0, a0, 6
        ret
```
the `6` in the output doesn't make sense, it is coming from an insufficiently-protected `Bitwidth - 1`. 

@MitchBriles, a student working with me, has the following candidate patch. it certainly fixes this case but we've not fully vetted it yet. actually, if nobody is in a rush to fix this, Mitch would like to be the one to submit the PR for it.

```
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 4a1db80076..7a5ebf74c4 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -18740,6 +18740,10 @@ static SDValue foldSelectOfCTTZOrCTLZ(SDNode *N, SelectionDAG &DAG) {
   if (Cond->getOperand(0) != CountZeroesArgument)
     return SDValue();
 
+ unsigned BitWidth = CountZeroes.getValueSizeInBits();
+  if (!isPowerOf2_32(BitWidth))
+    return SDValue();
+
   if (CountZeroes.getOpcode() == ISD::CTTZ_ZERO_UNDEF) {
     CountZeroes = DAG.getNode(ISD::CTTZ, SDLoc(CountZeroes),
 CountZeroes.getValueType(), CountZeroesArgument);
@@ -18748,7 +18752,6 @@ static SDValue foldSelectOfCTTZOrCTLZ(SDNode *N, SelectionDAG &DAG) {
 CountZeroes.getValueType(), CountZeroesArgument);
 }
 
-  unsigned BitWidth = CountZeroes.getValueSizeInBits();
   SDValue BitWidthMinusOne =
       DAG.getConstant(BitWidth - 1, SDLoc(N), CountZeroes.getValueType());
 ```

</pre>
<img width="1" height="1" alt="" src="http://email.email.llvm.org/o/eJy0Vl-Pm7oT_TTOy4jIGALkIQ_5061WajdVs7_-pH2pDAzEd8HOtc2m2U9_NSbZZrftfWh1pQgCnjk-Z2YYj3ROtRpxwWYrNttM5OD3xi4stri3k9LUp4XfKwfNoCuvjGbJkvEly_j5x5c1Vp20CCoHlvKue-qnlffPU5UzUdBlDSoG1ffStkzMyZucGqUvPk0wBCZmnIk5sHzF-BLoWQBLNlDJrvsV_Nkr7NHIzuG4RfBOgreq-gPg33Blyy8WabBw2GHlCYGcAlgO_HwnFsHcoj8_p6Qh37yJg3LQovdKt9ArV5n-oDqsoTyB3yN8vt2tv2QpE6sVlLJ6RF2DdD9Gszm_4nNjFeNzGXiM11gU41Lln6-Xwjup67f22bhi0b_ZhAixjGcs46B04GcGfxg81AadZiL30MtHBIeaIroG5UE5qExP8hprepAalHZD06hKofbdKTpY47HyWBP2Svmjqv0eIohZxqcw5p2l_KPy1X5lVYcuUAXnhxq1h6OxjwR_VH4Pfdh2L11g15iuM0darEhnLT3CQfpqPyVmFVovle5O0KhvSB7EVTqEcvBwRCbyJwRtPDRD153gCT2xVB5O6KcgKz_IrjsFnQ1oQ1VPcpUGCXZwe_CGoAMwWQUJcDRDV0OnHpHWSxzjqMOTG8pe-fDm02dojAXlp-cQXH87qmkgilrlQTJxQ9VNN1UycXMvbYueiZtQOpf77Q67D-aIVul2Wh0OUP6eHxWsrvEbpDKuy4LzPJtOcznDssnTKoWY8yylQo-i6He5kVixGn9_wJOlnKUcorjIU6rrDJhYXR5iDud156VXFew2X2Q3hJKpd-HD3jbr-_uHrV3ff3hgotht7kyNwMTyjnI52iijN8v3wES2Wb6_bkJUEUwUa6PriCXvWvTbA1qpayaKsVuJmHrI2gzaP6A16Ja2HXrU_tKJIPSOweoLNyYKWkvCDmOQYNChD9ewUv7_4cN5gzpt0QfvnXrGW71S3l3jEMaZKxOxcp8ohttGfE0EE8UFlMzHFkzm_8aLsvZK_ysi20Nl6rM9ESWut7sN9a5kSdH--vDu8_br_-42725eRROuJQWJm-V7Qrwb8V6BhPRsPpjqNYEgYk14PwvP_elwESLWv0rLKPGqrgom1vm5rmZiLLL_sKz-jDiMhw-VTgR_XDkAL-IuCB-VHtxWY0jtOW9wydTaaOcl0Xkpq9Dkr5J196OIn8p80XPVEif1IqnnyVxOcBHns1lRzNMsmewXdZrFiHmcFLzJmzTmRVJWGa9jTOZ5irOJWgguZrwQIp7zVCTTep7lOG_SnJc1b5KEpRx7qbppmCKMbSfKuQEX8WzG43TSyRI7FwYhIcqhZYIKgf6P5zVLltSioi8vCy_nvAyjkRA0QdkFwUfl0DoaWJTz7vuGXvkOF1a5Knp6mQO-jwtgGqDpJrLYSTqjzMGrXj0H_Mlgu8Xe-0MYG8QNEzet8vuhnFamv-qutPvBmr-wou4aJDombs4qnxbinwAAAP__OT75sQ">