<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/150875>150875</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            [GlobalIsel] Assertion when generating code for ptrtoint with vector operands
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            llvm:globalisel
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          arichardson
      </td>
    </tr>
</table>

<pre>
    The following IR when run with `llc -mtriple=x86_64-linux-gnu -global-isel -verify-machineinstrs`
```llvm
define <2 x i64> @ptrtoint_vec(<2 x ptr> %p) {
entry:
  %addr = ptrtoint <2 x ptr> %p to <2 x i64>
  %ret = xor <2 x i64> %addr, <i64 -1, i64 -1>
  ret <2 x i64> %ret
}
```

triggers the following assertion:
> llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp:1428: virtual MachineInstrBuilder llvm::MachineIRBuilder::buildInstr(unsigned int, ArrayRef<DstOp>, ArrayRef<SrcOp>, std::optional<unsigned int>): Assertion `(TypeSize::ScalarTy)SrcOps.size() * SrcOps[0].getLLTTy(*getMRI()).getSizeInBits() == DstOps[0].getLLTTy(*getMRI()).getSizeInBits() && "input scalars do not exactly cover the output vector register"' failed.

</pre>
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