<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/150304>150304</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            RISC-V assembler should accept compressed shift hints with 0 immediates
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            new issue
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          Timmmm
      </td>
    </tr>
</table>

<pre>
    Currently if you try to assemble any of these instructions Clang will complain:

```
asm.s:49864:13: error: immediate must be an integer in the range [1, 63]
c.srli x14, 0x0
 ^
asm.s:50440:12: error: immediate must be an integer in the range [1, 63]
c.srai x9, 0x0
           ^
asm.s:188:12: error: immediate must be an integer in the range [1, 63]
c.slli x1, 0x0
           ^
```

These compressed shift instructions with a 0 immediate are HINTs, but I don't think that means you shouldn't be allowed to assemble them. You can assemble `c.nop` hints for example `c.nop 1`.

There probably isn't a practical use for this yet seeing as no meaning has been assigned to these hints (they are [designated for custom use](https://riscv-specs.timhutt.co.uk/spec/riscv-isa-release-ffbb6fa-2025-07-17/riscv-unprivileged.html#rvc-t-hints)), but it would be nice if there was some valid syntax for representing them.
</pre>
<img width="1" height="1" alt="" src="http://email.email.llvm.org/o/eJyslM-O67YOxp9G2RA2ZMl2koUXmTk3uLPpoh0U6FKWmVg9smSIdP68fSFnMJNBga5OICCJTOtH8vsoQ-TOAbETzYtofmzMwmNM3bubpmna9HG4d69LShjY38Gd4B4X4HQHjmCIcOo9ggl3iCfgEQnBBeK0WHYxELx6E85wdd6DjdPsjQtCH4RcVys_ljwYmkoS-lDvd20t9KHSQh8AU4op_3DThIMzjDAtxNBnJLjAeMYELmQyJBPOCKJ5qYR6hVaL5oeQB1tS8g5uVZ135S3DQDT_e2I2sq5lZqpfyDQObvsn5NfnO7za7X4x2q_l_gf6ue9CHt5X1bI6CYlwABrdib_LeHU8ggH5lJlJCP9_--2dMqlfGN5giEGoLQOPLvwEHg3DhCbQ6hka4-KHR0AuyPt4xeGbjXjEqYS_4gLWhK9t0UpbhjiLVsLoAhOcYgK8mWl-egqVaGX5WVJCmFPsTZ9dSw-sgTkZy84aDwvhegyPjuCODITowhkMQYhr2vnfaAh6xDWZPCVrvg-bPzIRascj3tduiOZlwBxmGIf1cLsQxymzsjpqNzLPWXShjkIdkyN7KWhGSyW7aVyYSxvL5adQx7z7GeLIFAk9GsLidOr79mQKJVVTyG1RbT_DljAnd3EezziUI09eKJ0utuBizVWo_boeajmGaxYkaxGcxTzavLbtaggoTggX490AdA9sbms5CbNFMHBuzSrWZuj0sNd7s8Gu2jZay6pq9WbstlrX2Ld7bLdta7eV0bVuG7vXO2yx3jUb1-UK5FZpJWUrdXnSTWMqu9_t-nZopRW1xMk4X3p_mcqYzhtHtGBXNVLLeuNNj57WS0upgFdYnwql8h2WuvxS0S9nErX0jpi-jmHHHrvf3_54Lf78NFn68CcYa3Hmf4_DQ-51Dp6mgDZL8t13Wc-Ox6UvbZyEOmbqx1cxp_g3WhbquOZKQh0_irl06p8AAAD__1IWx48">