<table border="1" cellspacing="0" cellpadding="8">
<tr>
<th>Issue</th>
<td>
<a href=https://github.com/llvm/llvm-project/issues/148987>148987</a>
</td>
</tr>
<tr>
<th>Summary</th>
<td>
[AArch64] Avoid materialising bitwise immediate arguments by decomposing into 2 arguments
</td>
</tr>
<tr>
<th>Labels</th>
<td>
backend:AArch64,
missed-optimization,
llvm
</td>
</tr>
<tr>
<th>Assignees</th>
<td>
</td>
</tr>
<tr>
<th>Reporter</th>
<td>
Kmeakin
</td>
</tr>
</table>
<pre>
The `ORR`, `AND` and `EOR` instructions only accept immediates in a specific form. For immediates that do not fit in this form, we have to materialise it with `MOV+MOVK`. However, sometimes instead of materialising, we could decompose the immediate into two immediates that are accepted:
https://godbolt.org/z/oYnbYj9We
(The `volatile` keyword is required to prevent LLVM performing constant folding)
```c++
#include <cstdint>
typedef uint32_t u32;
u32 src1(u32 x) { return x | 0xF0'00'00'F0; }
u32 tgt1(volatile u32 x) {
x |= 0xF0'00'00'0;
x |= 0x00'00'00'F0;
return x;
}
u32 src2(u32 x) { return x & 0xF0'00'00'F0; }
u32 tgt2(volatile u32 x) {
x &= 0xF0'00'00'FF;
x &= 0xFF'FF'FF'F0;
return x;
}
u32 src3(u32 x) { return x ^ 0xF0'00'00'F0; }
u32 tgt3(volatile u32 x) {
x ^= 0xF0'00'00'00;
x ^= 0x00'00'00'F0;
return x;
}
```
```asm
src1(unsigned int):
mov w8, #240
movk w8, #61440, lsl #16
orr w0, w0, w8
ret
tgt1(unsigned int):
sub sp, sp, #16
str w0, [sp, #12]
ldr w8, [sp, #12]
orr w8, w8, #0xf000000
str w8, [sp, #12]
ldr w8, [sp, #12]
orr w8, w8, #0xf0
str w8, [sp, #12]
ldr w0, [sp, #12]
add sp, sp, #16
ret
src2(unsigned int):
and w8, w0, #0xfffffff0
and w0, w8, #0xf00000ff
ret
tgt2(unsigned int):
sub sp, sp, #16
str w0, [sp, #12]
ldr w8, [sp, #12]
and w8, w8, #0xf00000ff
str w8, [sp, #12]
ldr w8, [sp, #12]
and w8, w8, #0xfffffff0
str w8, [sp, #12]
ldr w0, [sp, #12]
add sp, sp, #16
ret
src3(unsigned int):
mov w8, #240
movk w8, #61440, lsl #16
eor w0, w0, w8
ret
tgt3(unsigned int):
sub sp, sp, #16
str w0, [sp, #12]
ldr w8, [sp, #12]
eor w8, w8, #0xf0000000
str w8, [sp, #12]
ldr w8, [sp, #12]
eor w8, w8, #0xf0
str w8, [sp, #12]
ldr w0, [sp, #12]
add sp, sp, #16
ret
```
</pre>
<img width="1" height="1" alt="" src="http://email.email.llvm.org/o/eJysV21v4jgQ_jXmy2iRcV6AD3yA0uik3b1Kq1NP--nkxAN4m8ScPYF2f_3JSQgvLS89YUWhlh9mnmdmPEylc3pZIk5YNGPRvCcrWhk7-VqgfNFlLzXqbfLXCoHF_OnHDxZzJh78ZvrnnMUcZKn87vHJH4EuHdkqI21KB6bM30BmGa4JdFGg0pLQgS5Bgltjphc6g4WxRR8SYw8htJIEykBpCBaa_FdopV0N9u63CCu5QSADhSS0WubaIWiCraaV5_P96ZmJ2fen568s5n34w2xxg9Z_15kCSRc1EUcoFZjFgRVdLlsPmalyBQozU6yNQ6AV7jmCLskAbc072tJiKxoVC6aM-2dFtHZ-JxImkqVRqcmpb-ySieQ3E4n5WaY_f43_Rg8XozbeG5NL0jn6yL7g29ZYBdqBxX8rbVF5-WuLGywJvn17_g5rtD5CulxCZkpHsiRYmFzVmsbedMybJ2Ni5h_vLdBlllcKgQUPmSOlS2LBY8Ob3taocAGVLikQ_xBUgWDBrDmsAgHOZgMmRv7PVybGwIYzsEiVLeEV2PAB-GvCmRjy7pVwFsyADeetBVqSt7DTCoemGJ8CQGOJBfP3xnhD5gTEP_DYonbcWhE1i70UcV6KiG-SIq5LEfGHUpLkSEuHSpqz3etmLcF5LdHjTVqC61qix4_TcpyXHeqzedlVa6Or20pXMD7dVV5Zty_lL6Qv8vrGQWE23ipsR3W3EoEIeevJr8JsXo6O40EY1o0td7nfD-IDtLG2MVYj2vfoAGCR2uvS1PLHnNrlqrT5XNfdaN0yaDw6OnTFotn-XLBofmAmV_ZQ4QVkR3_UEm9g_HXB63XIjW41ehf3n_PcubwaG6nU-RB3ydrd90vJ8r9uB-T5nnyz-Am2K47jGC8WZ6rlKgFfLR_KOI3bPQrmRO1FFZ8rleuo877fR_p_lOn9aia4lrK79h40n-g9V6ld7D23V9Ttl7-jf6b3nGb1no3ngu-jVnvnIroU2zZZux-ynpoEahyMZQ8ng2EkYsHjMO6tJlkcZWEaYhYMBnEciiAbyXGaooxShTwe9PREcBHx4SASAQ953A8HfDEeZGMMJQ-yUcRCjoXUeT_PN4UfNHvauQong3A0Hg17uUwxd_XIL0Qqsxcs_bA6ndpsFYdMCCYemBCFdg7VF7MmXejf0o_13Zk37DfRvGcnfvMlrZaOhTzXjtzeL2nK638udsajOUw3RqvjoRtSTdt6iO9GbGmXVYElOUjfujncQ-vZW-zPe5XNJycjtqZVlfYzUzCRNFTrjy9ra35hRkwkdUAcE0kbk81E_BcAAP__k3tu1Q">