<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/147358>147358</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            [AVX-512] Missed comparison->discrete-masked-OR fold
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            new issue
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          Validark
      </td>
    </tr>
</table>

<pre>
    [Zig Godbolt](https://zig.godbo.lt/#g:!((g:!((g:!((h:codeEditor,i:(filename:'1',fontScale:14,fontUsePx:'0',j:1,lang:zig,selection:(endColumn:22,endLineNumber:1,positionColumn:22,positionLineNumber:1,selectionStartColumn:22,selectionStartLineNumber:1,startColumn:22,startLineNumber:1),source:'export+fn+lower_simd(x:+@Vector(64,+u8))+@Vector(64,+u8)+%7B%0A++++return+@select(%0A++++++++u8,%0A++++++++@as(@Vector(64,+bool),+@bitCast(@intFromBool(@as(@Vector(64,+u8),+@splat(!'A!'))+%3C%3D+x)+%26%0A++++++++++++@intFromBool(@as(@Vector(64,+u8),+@splat(!'Z!'))+%3E%3D+x))),%0A++++++++x+%7C+@as(@Vector(64,+u8),+@splat(0x20)),%0A++++++++x,%0A++++)%3B%0A%7D'),l:'5',n:'0',o:'Zig+source+%231',t:'0')),k:61.31071190951432,l:'4',n:'0',o:'',s:0,t:'0'),(g:!((h:compiler,i:(compiler:z0141,filters:(b:'0',binary:'1',binaryObject:'1',commentOnly:'0',debugCalls:'1',demangle:'0',directives:'0',execute:'1',intel:'0',libraryCode:'0',trim:'1',verboseDemangling:'0'),flagsViewOpen:'1',fontScale:14,fontUsePx:'0',j:1,lang:zig,libs:!(),options:'-mcpu%3Dznver5+-target+x86_64-linux+-OReleaseFast',overrides:!(),selection:(endColumn:1,endLineNumber:1,positionColumn:1,positionLineNumber:1,selectionStartColumn:1,selectionStartLineNumber:1,startColumn:1,startLineNumber:1),source:1),l:'5',n:'0',o:'+zig+0.14.1+(Editor+%231)',t:'0')),k:38.6892880904857,l:'4',m:100,n:'0',o:'',s:0,t:'0')),l:'2',n:'0',o:'',t:'0')),version:4)

[LLVM Godbolt](https://llvm.godbo.lt/#z:OYLghAFBqd5QCxAYwPYBMCmBRdBLAF1QCcAaPECAMzwBtMA7AQwFtMQByARg9KtQYEAysib0QXACx8BBAKoBnTAAUAHpwAMvAFYTStJg1C1aANxakl9ZATwDKjdAGFUtAK4sGexwBk8DTAA5DwAjTGIQAE5SAAdUBUI7Bhd3Tz04hNsBPwDgljCI6KtMGyShAiZiAhSPLy5LTGsshnLKghyg0PCoywqqmrT6hT72/0787siASktUN2Jkdg4sGgCAanQFVAB9WlRRWjWAUgBmJwA2STXVNbwADlPsNYABPYB3cO2ElnQIU4urjd7o9jgAmACsGimaz2B22bgYzDY6G2THQ6GIxwA7AAhI4aACC2EExAAniB8QS1mDwVxjicACJrNHoekA663B4nJ5HCEaUhs%2B5rAC053BAqFovFnJFYold1l0slcplUvlivVatVKuVSoVWt1mp1%2BuNGu1erNhvNRotBpNttNdst9ptrut7qtnpdHu9Xud/qdgcdwYdobdfqDYZ9AZD4d98ZjUYjsfNj0p1N54NB9KZeGQLBiazctAIbMuHOB3Jp9UFCtB53V9cbDZlTdbLaFbc7HbrPbWXd7zaH7eH3dHg5Hk7HU4n07ns4X/b7A6X49XM/X883i5Xu%2BX%2B7Xe8PB43R9PJ63Z8vF53N%2B3S7ThIzEJOObWJDLgM5IMz/NraxOUF1UA4CgJlEDwLAoUIOgqCFRg%2BC4IApCEOQ0D0MgjDYKwxCcLQzCCOwwjcOI/CiPIkiKLIyiaOoujUIYlCmLwxiWOY0jWI49iqM4njuNo3jEMfKkaSuU4mWKGxPwrLgfwhMD/nLIEuR5F8BUUr9K1UyF0zWYhMFLDSKxU0TKSOLEGUpDgZloThwV4LwOC0UhUE4HwfAANQAWTWABJAAlNYtnmRYwROHhSAITRrJmABrEBIX0ThJAc6KXM4XgFBAfkoqc6zSDgWAkDQAs6HCchKBKmIyoiEwbGIBFYr4OgCHCLKIBCNKQn8SpyW4XhuuYMkAHkQm0Epcoikq2EEYaGFoPrnKwEI3GAJwxFoLL%2BtILAWEMYBxDyna8H00pTEwLbnMwVQSjcVrOAi/xWtso7aDwEJiF6lwsDSghiDwFgHt4c7iBCeJMAZTA9qMN6jGimYqAMYAFA8vBMDeYaYkYIGZEEEQxHYKRcfkJQ1DS3R6gMOGTHMfR3qyyAZlQGJmi24VhtfYUWGQGI3HEgAvBgQfslyQf%2BrAGYgGZJOaBwGGcVxam8eWOjyAp0niRIBAGOpYk15pVa6CIhkaCayhGHW9Bl822kNiZjd6NpLaGEY7fVrhpbmBZCZsuzUqO1yOBhWhkDWCA/sa6EIFwQgP15cKpl4XKtCmOKEv5F6UtIRznMDzLssi%2BHfY4UF/dzjLC7y1PSBBhJ7EkIA%3D%3D%3D)

Idea:

```zig
// For each letter, check if it is uppercase, and if it is, make it lowercase.
// otherwise, leave it as what it was before
export fn lower_simd(x: @Vector(64, u8)) @Vector(64, u8) {
    return @select(
 u8,
        @as(@Vector(64, bool), @bitCast(@intFromBool(@as(@Vector(64, u8), @splat('A')) <= x) &
            @intFromBool(@as(@Vector(64, u8), @splat('Z')) >= x))),
        x | @as(@Vector(64, u8), @splat(0x20)),
 x,
    );
}
```

LLVM optimizes to:

```llvm
define dso_local <64 x i8> @lower_simd(<64 x i8> %0, <64 x i8> %1) local_unnamed_addr {
Entry:
 %2 = add <64 x i8> %1, <i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65, i8 -65>
  %3 = icmp ult <64 x i8> %2, <i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26, i8 26>
  %4 = or <64 x i8> %1, <i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32>
  %5 = select <64 x i1> %3, <64 x i8> %4, <64 x i8> %1
  ret <64 x i8> %5
}
```

Emit:

```asm
.LCPI0_0:
 .zero   64,191
.LCPI0_1:
        .zero   64,26
.LCPI0_3:
 .zero   4,32
lower_simd:                             # @lower_simd
 vpaddb  zmm0, zmm1, zmmword ptr [rip + .LCPI0_0]
        vpord   zmm2, zmm1, dword ptr [rip + .LCPI0_3]{1to16}
        vpcmpltub       k1, zmm0, zmmword ptr [rip + .LCPI0_1]
        vpblendmb       zmm0 {k1}, zmm1, zmm2
 ret
```

Should be:

```asm
.LCPI0_0:
        .zero 64,191
.LCPI0_1:
        .zero   64,26
.LCPI0_2:
        .zero 64,32
lower_simd:                             # @lower_simd
        vpaddb zmm1, zmm0, zmmword ptr [rip + .LCPI0_0]
        vpcmpltub       k1, zmm1, zmmword ptr [rip + .LCPI0_1]
        vpaddb  zmm0 {k1}, zmm0, zmmword ptr [rip + .LCPI0_2]
        ret
```
</pre>
<img width="1" height="1" alt="" src="http://email.email.llvm.org/o/eJzsWVt3qrzT_zT0htUuCEcvehFOiuez4s1eASJEORWCqJ_-XaCtte3u02e_z_pfbRdLk8zkl8nMZDKDqChIkGD8zEgaIxkPqKRhmj8vUUR8lO8f3NQ_1bQNCdh26rtpRBnJYIAaUpoVjAAZYDHAOpPgKajJTxFtRoSgofEMUBmg_r4TMgL0Uh-bPqFpzgCdNFR1SyKcoBg3PYVngMIAfZsmdOahqB7lxevAosDj44WNu7DtajID9Agl9VpnEjBAL3CEPUrS5IKPE19PozKuuwAwQMeJ3ycJHpaxi_MrQJYWpJ5yz_k6-on9bYkZRTm9n3RP-zz1ixlfMbZqQlrm3lUx-JilOWWAtk0YoEVphfNfBYl9BqgXnWiMyC2x1-hWlWudMUAr1Qap9T1ZY4Ck1F9cg_P65JiWeXKZetlVY8kPXO-fGk__loMROVTUMF9I46ZpdNn4hdElVEcFvXCThFp5GmsNj_odzHVTV5Aii9BF7tq1Lu6o3JQCJKEWWDAYoB3fxoD8_SbuN_TfiLb5QjTzXrTW6-xvZDtezan_g7K_FoU7Au7H63zF0KolfnUlSTFed6RHFzeWLgc3uTvG6aW3qY-vdnX6ix2Eazyg7_mv4u0ZAcr8k8BzCs-3uJbEiwK4rSR-s9KlUwc17gtw_evQFWckwu8C19uIAM8cL9aHe0siivNLsFTdu5VdkqD8dBfkLkMjd1efrPcEL41jnNBREp3uMHzsloGOoqi4Y_dxjJIgwve8JK_D0AEXd8P4iL2S3gdbklAc3XFFxM1RftJT_x6U5iS-m3rAuZsW2LhIQJLgoyq3EQqKJcHVKMPJfxbiI-IW7wxUL5Rmdcy9bvYx9rKyOTvn5IBziQHaI0V5gOsAelTlX7L4GJGkrA_L42iKI4wKbDWxpvGSA85z4uOPa3xzs_A_vVj4P7hXPpP-4Vrhf3Sr8D8-mQzQGsVr3BMvPvHN4VRfL_K3g9r6_qwK6pOstoCqci1OVCXl01GtXYvnuD87tO92Av7x5H81-YDz4mJasR7gYP1IWr-_HHyXD0XRIf6QEJ0ZAY6cfhBCS3vxpYl-hE41drSBHmtTX-tDi5_oHkRjU4eDc6XRAVTgpLLoYKKd4DRo9ejEMeGpIC43WUP9qGoa7KVaModwATtZBQcHaDnzGe0GvM4jODyifdTawHll9HY-bFsLCnti0cbHSturxhxCyajgbt62J9CUZhD6C21hK1roC_MzJ4bDQhtXRhDtdFvu0UH7NAsh2RAYzsb9k9Sft4siTPq9IDwF3FhPT9XLS5zP5XBeq9riFFUpCJzt6WIIuns_EIt2oEOUTKwl1FqraDpd7VZwEWhxt4JgNl8vh24FjWhcDB2ojR1N8EbAjJKJvRDLfOcraWsXwBjqRZvE6Aw0ANzAORuO3AbzzkRu28cKKhCGtoigrgPTPEKYEE2dzPjYqJbHHfGg3s2HnRTvoSwLmph0pY5uokVY1M6qSTnUOUnQ4IuVHqykazlp5PMRV0ReFi0OETksEV32yuUsXa4oH2d8M60ctkse58PwMJymVMuGlA79grYympdUeaFJ5nfK1rr0GWC9-IHnV46fuv72xXA2LbgxRL-lbnYLZ1dshzsu44eSONRavQ1uT_oaQWePQtsdlJ2RJnSz1sLSqSYJy5bnGpto7rt9ZLme0nHzsbta-8oZdRTcEfxOIHX2SmchJpySFOKaAZarQHktttYDBlhrVRWItC6bHaybb2WN1bEmCtPWuCsLG_VgScKwoQgzZR7aZ7M7GrmrrtEPBpI9ODPAGuboOFpY_AKKetCNTKPqw3Rhj4IX3ZoGzVxdtGGmm6MJZ3CDYGc4veqoe_3JWddHVbXzRjYDLJ2M7T3p9e0TQaO03C1sJ9LjfnUkq5HD7Va22CIvAzHZlcNU2JmDbW-PZuVCjFe99nFc5f1gW4UDgwFW0rfNcipZqrZY5K0evzhZ3HnlhAOrb8x6xwU3781GfbO9yIxgE6XzsFqK_Wqkc4twYYqdagvhcAJX8xXUuhBGQ4cm8dSppqNOOIP2fJp3Y6jlpmavuXnYhZ7cWw_EdWBpcLtPXzz5PDOCFdwbE1jIHd0Le1ovtk8pMSu3bWuWk4ujQO_o_Z6t6cPeJFFn2WklrsOydAZ72NlPYs7MvJTsX4BpOqhtpeM86VWmLbRhtzpaab_fqJXafbgyB452NE4JUjscl83Nqu8mg2o5me28ZT6ChAHWcUWLVEFGZXaJJUdVYcyCkBiVFXSo6ClE03F3ADdz2HoZDOVdm8TOCxw40ILqQRsY2EHO3rHbG9M0J8eO05t62313whszYSoHg1F73hlsp8LL6QQ30aTdjQkQlyHdOotVe9K2hY4ZwIMWTLZFdJpsG8lz2HaC9qY7QlrVbnvLI4pVvBrtTjDjEjK1NdgeZc6el7IlknU73CMdncJ2Z9XSIhWA_ZBsdr48zPqobTrKdpmHmRtrG31TlOfFy4g_jbRwFe6NlV7H4gLJpm1Vk2DMS14vi8R1j-rxqGceJEteUHt6TgbGuV8UpBGus3XERR3A_fOurysnfjzTtLCrmHsbXrPu29f1OrB9jOrAf7kbZO7y1Dcjd70NWCvNWYy8kI0wpU22yHoh9vYs2bKEsqRgyyzDuYcKXNNQ4r9R6n6M9rjuNfVdzfR0g05piPOKXCZGGB0aTlSwVYho3axQwbp4m-aY4eClXmS3CfupVmQ_1QPsa534OxLLKBrDQZZl2UtVyN7VhBxkL6XfhaX-_Lb2YG9lHvuHRd6ruA3ArYpS4Nt9zjKCzggGe2zaQH4n2FW4_-dSm_dLma9L3Uqn23pHllH0b9Tx1QL3ZRgH2eMNsx4UamMwivHeDS9e2aQrdS4ckzMuWJp-9tc6Y2E46OMtSTDrF-mvKPVQVKtMFtkjS1RGMGtp7hznAxVIXCPzx9E6DWQbvF9lkqAY-7-Q7-dX_zETeqmBOFgzA7ZWHPL9L3EadKKyj7JUd_62_rb-xy3BbM5cfQk0nkq8OGPLiH52V3BzVyBfEf42_jb-VePmbmLjbmn-bVxsXnaxfxt_G_-2cXM0qXG0SyJ3czb-6mwC89UVL345yjeQOf4iOEq_S1bMmNDP-Qkq6vTkqa-Pbe4Xd80Wns44T1mWbXImvsXfOPgrx_Vzx9gkflc-4QNSTRcAw8F3aY5wlyV--jBA-JAXcZA9ZMj3XZY9x3GTEp3jmL_-VmnusxnNWUbScpKxDNDYt31JxjupD1nN2oCA9yD-NxBCDaFoPE15-aLeG5oXZxEt3Wt__yoQ98-C8R8FcyOc-PErVA1SJ3N7vl7yfru1MmsP-GzoWZiWkc-6-IfWvrPln5sc_BbuvzD8m4Ya-7_Tww-0_Mn8vzHYDzzpk8Fu7vjRUD8QDNyjfbDmg_8s-C2hhR7wM69IfIvnVEF8CJ_BVlHEliirriv5koc41-UE31VFJHCSj4QH8gw4IHEKp_CKJEjik-zJynaLJAkJSMZbmRE5HCMSPTUvVNM8eCBFUeJnXlQESX2IkIujovnvGoAEV2xDZUAt70P-XE96dMugqK1EClrcYCihUfOnN1yuHyW-nsAOSFFgn_XSOEM5KdLkkRFMnxRejil-jFGxx_7jaMpu08h_KPPo-f6db0BoWLpPXhpfXwBffx6zPG3-zAFWI17BAOsq_-EZ_F8AAAD__yjuZRE">