<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/144454>144454</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            Passing/returning structures in scalars does not handle poison
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            clang,
            clang:codegen,
            miscompilation,
            llvm:ir
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          hvdijk
      </td>
    </tr>
</table>

<pre>
    Originally reduced from an AArch64 miscompile, but I believe it applies to most if not all targets. This example is for x86_64:
```c
typedef short short3 __attribute__((ext_vector_type(3)));
typedef struct { short s[4]; } short4;
short3 f1(short s) {
  return (short3){s, s, s};
}
short4 f2(short s) {
  short3 x = f1(s);
  short4 y;
  __builtin_memcpy(&y, &x, sizeof x);
  return y;
}
```
Compiling this to LLVM IR produces:
```llvm
$ bin/clang -emit-llvm -S -O3 -o - test.c
; ModuleID = 'test.c'
source_filename = "test.c"
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) uwtable
define dso_local double @f1(i16 noundef signext %s) local_unnamed_addr #0 {
entry:
  %retval.sroa.0 = alloca double, align 8
  %vecinit = insertelement <3 x i16> poison, i16 %s, i64 0
  %vecinit2 = shufflevector <3 x i16> %vecinit, <3 x i16> poison, <3 x i32> zeroinitializer
  store <3 x i16> %vecinit2, ptr %retval.sroa.0, align 8
 %retval.sroa.0.0.retval.sroa.0.0.retval.sroa.0.0.retval.sroa.0.0.retval.sroa.0.0. = load double, ptr %retval.sroa.0, align 8
  ret double %retval.sroa.0.0.retval.sroa.0.0.retval.sroa.0.0.retval.sroa.0.0.retval.sroa.0.0.
}

; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) uwtable
define dso_local i64 @f2(i16 noundef signext %s) local_unnamed_addr #0 {
entry:
  %vecinit.i = insertelement <3 x i16> poison, i16 %s, i64 0
  %extractVec1 = shufflevector <3 x i16> %vecinit.i, <3 x i16> poison, <4 x i32> <i32 0, i32 0, i32 0, i32 poison>
  %0 = bitcast <4 x i16> %extractVec1 to i64
  ret i64 %0
}

attributes #0 = { mustprogress nofree norecurse nosync nounwind willreturn memory(none) uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }

!llvm.module.flags = !{!0, !1, !2, !3}
!llvm.ident = !{!4}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 8, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{i32 7, !"uwtable", i32 2}
!4 = !{!"clang version 21.0.0git (https://github.com/llvm/llvm-project 2692c3aa6760f1e4ea015f906926f63ec7dce044)"}
```

The definition of `f2` first does `shufflevector`, producing `%extractVec1 = <4 x i16> <i16 %s, i16 %s, i16 %s, i16 poison>`. It then `bitcast`s the result to `i64`, and because `poison`, unlike `undef`, always applies to all bits, this potentially throws away the well-defined first three elements of the vector-copied-to-array depending on exactly which passes run at exactly which time and how they choose to interpret `poison`.

In a larger example, I saw this go wrong in a context where SROA chose to split up the individual elements of `y` and then reconstruct the scalar by doing bitwise operations, where constant folding then kicked in for the constant `poison` element of the vector, but I believe this heavily reduced example already shows that the Clang-to-LLVM-IR translation is going wrong, even if the LLVM-IR-to-machine-code translation happens to produce the expected machine code so far.
</pre>
<img width="1" height="1" alt="" src="http://email.email.llvm.org/o/eJzEWF-P46jy_TTkpeTIxo6dPOQh3T0ttbSrWc2s9jUidjlmG4MFOH_m0_9UmLjTPTP7u6s70pWiBAOnqqg6PkCEc_KoEbds9cBWTwsx-s7YbXdq5N-vi4NprtvPVh6lFkpdwWIz1thAa00PQsNuZ-uuLKCXrjb9IBUy_giH0cMLHFBJPCFID2IYlEQH3kBvnAfZgjYehFLghT2id0v4s5MO8CL6QSFIB62xcFmX-7Jg-Y6lO1am06dm6c5fB2ywBdcZ66fvHPZ74b2Vh9Hjfs_4mvE1Xvz-hLU3dk8Qxtc545v4yR_uLXk71h5Y9XAzylYPBVs9sfwBWPU09RYTKDpsM8bXt9l8Q2CW7gAs-tFquA0Gl9WDo9TEr-ppMkSNaK6Alv_YXPR2AZY_RZ9z-HG0gOvteb8_jFJ5qfc99vVwDYkor-SX8fIS_MtvaFq43FmJIV_vw5ozztLdY6iu1EfwVCdv4Lff_vodXr7AYA1xwn2oklKnnp55AQepGX-uldBHSLCXPqFBSL5C8jmHxEACHp1fUmEp27-bZlT48hTWy3gVB3lFqTKjrXHfSoVa9Bin8NsUThUNjIJGeKHE1Yz-NgmTnuU7TAZepSzf5Tx80WP2_pFagXZlkci5kfE1y3cZXyftOo0tHbrKG7wskq807T4ObyUxOsYwMToZ9as2Z50oqcdLctTjBIkJeB517aXRsPPeUmKhH50frDladA60aS0iaGOxHq2jlrvqGrQZ9VnqBs5SqVjQHntjiQPaaCRSjWcvDgpZumuwlRqhcWavTC0UNGY8UKRFGkgmszKYDG8HacTFA-OrQM0A2I-aatDsRdNYYDxPI2VRe3ud-AAEsehPQi2dNWKZhkwIRRaiR6KkUPKoYX1DnLCWWk6Vk9qh9aiwR009j_QqSEr6JxiMdEaTAYp2iu4RZFlA-sEUD7ZcN7atwkkSPth6mxvelZ_4ufVTvT_BN7SGEFIo-Q3t9EJ6Y_GntjkZGbz9Li8fsvBxeJku_9vnkAFlRHOX9_8gEtKGmRu_Pqo3ufmfkp84Q8znv5T5sehL-SuYjBdvRe3_wjr7F2Reyv-HzsUbnVn-KHMOgQE_bkRk_ukW1PQ-H6SvhfOzuTmI-5i9ofXMlAoZ56v0ngDzBu5iVkk1q4dfTwHS4l7qROFRqGRKYXKWje9IifMnxnnKOKdp2iTeimGQ-pj04m6CtyPGOc6L-jUZrPGTpcPYtmgT2mjn6es4d9oXknoY56HLukzK4v14i8KPFt08ifGHujcnxh-pdVlPjfbi7NTq-8vUcA7nBp9al3V1sz5qfOf7iBqtrMPw_B7yjLboZR924mWrxNHFHSwjovMsnc4TWRZ_efzNo41oQDYT0--Qxb2X9G6M6HUzxzg_152w-1sGI_2K2Xz2Abl-Q_7x8gi_4QnVHZDPQP4BWN0DP_0DMP858KYrP4IV75fPOJ9OQie0jmSOZySDR9rs-LrzfggnKf7M-PNR-m48LGvTM_4cDlTTDxHtb6w98HLD61yIsirTNsMCRZqt2k1abnjZljnWVVNjWhThwMu_P9WxdPdnhxDEUAbRNS2wklSwTKGV1pHy08tYpu_UhuC0e4SzH50KQ8d3CvVBDvLHd9r2D-03mSnTJbx48B1qchKFhuKhPrDoRuVJWliZkrpMgQndwAFrMTqkgWhuGhu1kq-hOyj8DaHO4urubyp0OzlIH2IKh97BeNS01asr-M6aswNxFtcQxxmVSqZNpYmJ8x2pVFR7R5mliVFqajNIbBJvEmGtuEKDA-qGMmk03YJqr65w7mTdwSCcQwd21CD8hzEvewyL7cyZzF-h7oxxGLRWe7QDKe19BpZT2V80CFCkNPZ26aJ1voAT52m1RwNna_QRJE2tjfa0DZ47tAhfv3zekafJkRuU9DAOYX1SN_Ikm1God0tnZXolTlGsoZYWa6PjpYtwrhZKWDhcoTGUhoP0Z-kQzIBWEDVDHSb3ASm0h9aoZrqToIZXWb9iQ-HS1ZFszvPuE3AL631Bvr-2hiR0KE7y7t57u58KZVE0V7p8nYmIYlrEI73ZVFS6HCUvX8BboZ0K8UPIKUUb0koO8YSa7sIEjQgC96LuJKm0afCdhU4MA-pAznjrClC8DFh7bCACIQCdgVbY5aLZ5s0m34gFbrNqlWbZZrWqFt12XaxzseIb5GUlyjTLM162bZtVB1GlGU8XcstTvkrLrErTbJNVy5VYZWVbVHmGvCrrkhUp9kKqZZB6Y48L6dyI26woilWxUOKAyoX_FaLmTfo4P-U7CvSIeu6f_0YI6527g_TlO2mpZ_W0sNuggofx6FiRKum8e4vBS69w-4dwTpLH5-kgQHmf2EZ7KpFkIpyb9E0bD53QjcIoPYvRqu2_U2PGn8P6HePPMQWnLf-_AAAA__-Tz1sv">