<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/143825>143825</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            How to handle 64-bit data operations under RISCV32 in the backend
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            new issue
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          muxiff
      </td>
    </tr>
</table>

<pre>
    I am currently implementing a custom intrinsic instruction, which performs two i64 data operations under rv32 and returns an i64 type:
```
unsigned long long foo(unsigned long long a, unsigned long long b)
{
    return __builtin_riscv_dkhm8(a, b);
}
```

The implemented partial code is as follows：
`clang/include/clang/Basic/BuiltinsRISCV.td`:
```
def dkhm8   : RISCVBuiltin<"uint64_t(uint64_t, uint64_t)">
```

`llvm/include/llvm/IR/IntrinsicsRISCVXxldsp.td`"
```
  class GprGprPairIntrinsic
      : Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty],
                  [IntrNoMem, IntrWillReturn, IntrSpeculatable]>;

def int_riscv_dkhm8 : GprGprPairIntrinsic;
```

IR can be generated normally：
```
; Function Attrs: noinline nounwind optnone
define dso_local i64 @foo(i64 noundef %a, i64 noundef %b) #0 {
entry:
  %a.addr = alloca i64, align 8
  %b.addr = alloca i64, align 8
  store i64 %a, ptr %a.addr, align 8
  store i64 %b, ptr %b.addr, align 8
  %0 = load i64, ptr %a.addr, align 8
  %1 = load i64, ptr %b.addr, align 8
  %2 = call i64 @llvm.riscv.dkhm8(i64 %0, i64 %1)
  ret i64 %2
}
```

However, the following problems were encountered in the instruction selection stage：
```
...
  Continuing at 139534
  Match failed at index 139538
  Continuing at 141703
  Continuing at 141704
fatal error: error in backend: Cannot select: t11: i64,ch = load<(dereferenceable load (s64) from %ir.a.addr)> t10, FrameIndex:i32<0>, undef:i32
  t5: i32 = FrameIndex<0>
  t7: i32 = undef
In function: foo
PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace, preprocessed source, and associated run script.
...
```

It seems that during the selectionDAG stage when handling the load node, under rv32, the backend fails to correctly match the load instruction for i64 data types. So, I wonder if it's due to the backend's restrictions or how I can adjust it myself？
</pre>
<img width="1" height="1" alt="" src="http://email.email.llvm.org/o/eJycVt1u2zoSfhr6ZlBDJq3EvvCF7cRtgO2iSBa7exdQ5MhiS5ECScXN2x8MJdlumhQHJwhseTj_880nyhjN0SFuWLlj5d1M9qnxYdP2P01dzyqvXzcPIFtQfQjokn0F03YWW3TJuCNIUH1MvgXjUjAuGgXGxRR6lYx3jO_h1BjVQIeh9qGNkE4ezM0StEwSfIdBkmKE3mkMEF4EB-k0BEx9cBGky9rptUMmtqzYspti_C-2vcu5a7DeHYeP2nvGV-8cSMrlHXnF-Jrc3u5YsQWAMTI8P1e9scm452CiennWP5p2xfgq-8lGYpft7t4kxYrtfxq8dAk1dDIkIy0orxFMBBmh9tb6U2T3B7bbs_VYmbLSHRk_GKdsr5HxwyTZyWgUfQ9JxceHp_1_50lTzN_6orGGnC8AMLGFrDxaMrFnnPfGpZvlc6JenR_3cHleM86ZuP-9NnZTWPvS_pLkKHh4pI8JB0OK__9pdezGRDl_4w9AWRkjfO7C5y58kyaczcdpDAVcpGLPyh3FezaU6Csr7yjxN0K-h990zg6v_1i5I9__9l-xJSv68T9j7WMGwSR56lD1ViZZWSRn4n4c_tBq49I1SHLG71U02PzazodHUNJBhXBER8uAGpwPrbT29Q04LmZiB4fe5Q2DbUohUkTnjbPGITjfu5NxGnyXnHc4ZEknOvpn65W0eafYshi2hX6QEdXCeJkR_kZGgAfGRQHDoqBL4XUAHmSbudQ6ABN3IC2FIAfkR1pzdLCa9Kq_oxeTDzikOGbTpXCJ8kf16kq9eled8bLICVgv9RT-jwEYLxcfWXwYg2cLJe252YTIecbJfCKTMeli6jhFGvgo89Ak4x8RzRd_whfM4VODI6kQLXfBVxbbCCcMCOiU713CgBqMy6pXJA0RLY5PSR7xI9jN5_Oc2N4T9feZ_RMsxLoUy3zwVSbVQC2NRU1Hxmn8OSis3rNcLm4L8dEBuaxlkhYwBB8I4fmBCqik-oFOk2wvnfNpLIEEabGgr2FKqjnPLfPeSmPAGgM6hbTMw0QZX0VSX0MdfEsNN2E-QWHNxD2kRR7RIcgWH6gqJrZGcCb2BZFBfrNorEcpVZTKnIUYYHBtOJhkndtrncFDsX1wUI_LTce0osX227_ut0_3EPuqNQkkVP0RAnY-JEgempQ64gDGD4wfjiY1fTVXvr1QM3196oL_Tl3iBxNjj5HxQ37XjkSecaGCjE1ucApSYUZ6wC54hTGihuj7MIjJUsbolcmkFXoHUQXTpfkZK2-5juZEoEyNTKD7QPOmoGcA3m0_DxiEU4MOGum0nZTyqJzXOLV7uC1M2B8xkeEXqSnKh4CKLixtxuXZxzX0awLUdBuhS0acw5PPvA8nn4OYGkxi_DaC7pEcX0XL4oAxBaOGa4wP0PgTPGRWl_p7HxOYBO1rRFtPm3WY6Y3Qa7GWM9wsbpfrm_XqVohZs1kvlpWsV5XWelmWi1rdFsWilFiu1mpZ8npmNrzgZXGz4IXgpRBzIVe1VEoKXilZVUu2LLCVxs4z3fhwnOVhbxZLseLlzMoKbcyXPc4dniCf0pu5vJuFTcZJ1R8j8ZWJKV7cJJMsbr74U0YcTQbhZvmpMumDu1x-_ws-Mc7Yslkf7OafA3Ys42XD_woAAP__Ul1Tlw">