<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/143670>143670</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            [AArch64][SVE] MLIR's @setArmVLBits causing a seg-fault under QEMU
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            mlir
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
            banach-space
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          banach-space
      </td>
    </tr>
</table>

<pre>
    **NOTE** 
_I am still in the process of triaging this one. I suspect that this is an issue in either MLIR or QEMU, but I need more time to confirm._

**INPUT IR:**

```mlir
// repro.mlir

func.func private @getFlatMemRef_i32() -> memref<?xi32> {
  %c0 = arith.constant 0 : index
  %c16 = arith.constant 16 : index
  %multiplier = vector.vscale
  // UNCOMMENT THIS FOR VLS VARIANT
 // %multiplier = arith.constant 1 : index

  %vscale_times_16 = arith.muli %multiplier, %c16 : index
  %flat_mem = memref.alloc(%c16) : memref<?xi32>
 %vector_i32 = llvm.intr.stepvector : vector<[16]xi32>

 vector.transfer_write %vector_i32, %flat_mem[%c0] : vector<[16]xi32>, memref<?xi32>
  return %flat_mem : memref<?xi32>
}

func.func @main() {
 %c256 = arith.constant 256 : i32
  // Commenting this out removes the segfault
  func.call @setArmVLBits(%c256) : (i32) -> ()

  %c0 = arith.constant 0 : index
  %c0_i32 = arith.constant 0 : i32

  %acc_flat = func.call @getFlatMemRef_i32() : () -> memref<?xi32>
  %flat_vec = vector.transfer_read %acc_flat[%c0], %c0_i32 {in_bounds = [true]} : memref<?xi32>, vector<[16]xi32>
  %acc = vector.shape_cast %flat_vec : vector<[16]xi32> to vector<4x[4]xi32>

  %u0 = vector.extract %acc[0] : vector<[4]xi32> from vector<4x[4]xi32>
  vector.print %u0 : vector<[4]xi32>

  // Un-commenting this out removes the segfault
  // %acc_cast = memref.cast %acc_flat : memref<?xi32> to memref<*xi32>
  // call @printMemrefI32(%acc_cast) : (memref<*xi32>) -> ()

  memref.dealloc %acc_flat : memref<?xi32>

  return
}

func.func private @printMemrefI32(%ptr : memref<*xi32>)
func.func private @setArmVLBits(%bits : i32)
```

**TO REPRODUCE:**
```bash
cd <llvm-build-dir>
# Make sure repro.mlir is available in this directory!
bin/mlir-opt repro.mlir --convert-vector-to-scf --convert-scf-to-cf --convert-vector-to-llvm='enable-arm-sve enable-arm-i8mm' --expand-strided-metadata --convert-to-llvm --finalize-memref-to-llvm --reconcile-unrealized-casts -o repro.tmp &&  bin/mlir-runner repro.tmp -e main -entry-point-result=void  --march=aarch64 --mattr="+sve" -shared-libs=lib/libmlir_runner_utils.so,lib/libmlir_c_runner_utils.so,lib/libmlir_arm_runner_utils.so
```

**OUTPUT**
```bash
( 0, 1, 2, 3, 4, 5, 6, 7 )
PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace.
Stack dump:
0.      Program arguments: bin/mlir-runner repro.tmp -e main -entry-point-result=void --march=aarch64 --mattr=+sve,+i8mm -shared-libs=lib/libmlir_runner_utils.so,lib/libmlir_c_runner_utils.so,lib/libmlir_arm_runner_utils.so
qemu: uncaught target signal 11 (Segmentation fault) - core dumped
Segmentation fault (core dumped)
```

**DISCUSSION**

There are 3 ways to remove the seg-fault:
* Run natively rather than using QEMU.  
  * This will require an SVE-enabled machine.
  * Note, I am using QEMU 9.0.0.
* Comment-out `func.call @setArmVLBits` and use the default vector length, `VL`, instead. 
  * Note, this method is used in other tests that work fine.
* Un-comment `call @printMemrefI32(%acc_cast)`. 
  * This implies that there might be some allocation/de-allocation issue.

**NEXT STEPS**

I need to allocate more cycles to this. For now I am creating this to document workarounds that I am going to propose for https://github.com/llvm/llvm-project/pull/140573/.
</pre>
<img width="1" height="1" alt="" src="http://email.email.llvm.org/o/eJzEWEuP6joS_jXuTSlRcAg0CxY8NUj9moZuzQ4ZpyCek9hc2-Gcnl8_Kic06Qdn7p1ZjIQC2OV6flWuinBOHTTimGVTxvlOaCGLyB2FRMY5y-Y3ovaFsePuzs3O5G9jxieMTx4eN4vmF7Bksl2BqMB5VZagNPgC4WiNROfA7MFbJQ5KH8AXyoHRGMMKXO2OKD34QvhmQzkQGpRzNRITVL5AC_d3q2cwFv6-uH9hfAa72sMKNGIOlbEIXlUI3oA0eq9sFW9ZMqFP0G318PSygdUzS9uFdnOQNJ-qVDYQLxlfgsWjNfF5LZnsay1jesDRqpPwCKyfHNAvS-HvsXrG_ValnPFbxkcQsXQBFVYW9yydsXT5i_bSBbDhlCUTAMYzmQBL5yCs8kUsjXZeaA-0OAGlc_z1TtgbfEcZVj-RVnXp1bFUaMOJE0pvbHxyUpTY0gTjXh5mj_f3i4cNbP62WsPy8Rle79bwOnleTR42RNkSfuX5WYsPSpz1aCRuKRxu-0H9qi7VR64Ux3crP9mzL4XfVlgFBo0_Y1GWRgY_0xnyNh37xtmNGVnjBApO4FKWpypW2tvYeTw2m4FD85M4ZNPegGXzCxvi1PrSW6HdHu32p1WEgS7_1pKz0iGbMpmwbP57AXx2TX2w6GurP7nimrVsOP-MVdZPKqF0C8sWfaQVz74FVbM8AeLZwcvMVBVqf0nb2oPFypzQhfx2eNiLuvThTJAuRVmSdId-YqvXu6nyrg0az96jxvht8FubMY2aHRz9-RxJ3gP8PXGw50wtpNySPwP9B3WvJXSr7O9y-wNmTyi7GfiOGosi72rQwcg5D1pLhlOltztT69wFTiybelsjEQ7nV0HAZ7_D8dn4rmquEEfcSuH8J-WvA5Yq7Pte_xfLpv0v6ULM6qQrCH95K6RvVWDZ9NvE6HCCvTXVbwXBmffRKu3fRV7leNGtqYI6kn8F2JeaSOFrXHapS2cXdsD1bYzIe5dlPvkYniDhjMZg1n2gXbVQfBfdQeV33L5PqVbVHEMR_TPank82hej7ItO5EL_T-OjtJ-5dNa9x-lo4dsq792RubDpf3d1rfvMIz4un58f5y2zx4ao_E--EK1gykTmwdEbXQbSrVZlHubKtwTyFe_EDwdUWO41AaEpOQpViV2LT2igHubIBbW-M91gy2VG1XRJ5ZI6-ezqKpNEntD5q4Bl5Ezm576w7uafFD2sXWlKVpXPGh6hJg0jYKnInhM5fdVtVjA8hivDXUeg8ct6qHPOoQi9y4UWHc8sSomivtCjVvzBqQtTZsSiNlqrEqNYWA1EeEfwcRKY1zldHYHzA-ACgY72ttUbboYkQ6C6CCLW3b9HRKO0ji47SK52fjMoBoqgSVhYsnQv6HvTDivc2GM4Zn7oTNaUQuUJYzKNS7RxL56XaMb4s1Y5EbxvR29qr0sXOMD77uC__I4Ww1ReaK3h7fNk8vWyuwozxW0ioLvfoEXqElB59emT0GNBjCA2kn-4Wk_UCXL2rlAcBu_pALjTWU90ovD-6AGqqEwfli3oXS1OR5oSO5is6WvNPlJ7xZWigHdUUoXNQWpZ1jqGySStcATshf1BZxpglk7UX8gfkdXUkEckkiVkyerLmYEUFwh5qKpUk_n8N8--j3IR4xviU0Pz_ifQfWNVkaK2lqA-FBy_sAT3QoCRK6PWosK7xQB4RXhkNzTVBZRckjSLkRszJq1-o6GyX5notm6_Ws5f1evX40J1YNgVaBGERUvgp3hwho7m0zndW1GiTtpzgudaghVcnLN_AijBL-UJoqB1dfTROxQDtFTSBDdW1nzS_WfyjViRMw_p1ETWVJodKyELpAJrmxIPxFDMIo9-FKYziJCYYBS3aLjKiS5YNkut94iAJcK1dY1COjdvaZr1EffBFaJcGyesduYzPQGnnUeQxfNEpVOkKfWFyquC1Q8oEMI0XkGpZmDt_GvsD9q1ZxODSH5CkP3kps0ESf_KkqmjQcefploJXKQLVDsGZCiHcxgEgjC9zjC7_mwk47mLiYfGPDaw3i6d1FxPtFOzNmRk2E7F8kyUGhJAbYlgaC9r8bAIlLYpL7-MN5EaGJA--ELbpPoPagf5gArGhef5oHMLe2L9ek451WTK-7PWTbJgyvoxv8nGaj9KRuMFxb9gfDdIsHWY3xVgM0nR_m2Z73PN0l_d7OBJ7ng56WToa3A7yGzXmCc-SQa-XjPqjtB9jkonRLYo-prfDDHesn2AlVBmHsc_Yw01w6LjXTwfD5KYUOyxd-94jzPrN-w47bvuCg2P9pFTOuwsHr3wZ3pVMJqF4UUueTdevC-pn7-9Wz4wP3WdMgxRNWohLfkKtc2xeZtzUthz_99W9Nec05v8OAAD__3w1gOU">