<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/141907>141907</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            [RISCV] VSETVLI pass crashes due to "Cannot create empty or backwards segment" error
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            bug,
            backend:RISC-V
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          BeMg
      </td>
    </tr>
</table>

<pre>
    The error message
```
llc: llvm-project/llvm/include/llvm/CodeGen/LiveInterval.h:172: llvm::LiveRange::Segment::Segment(SlotIndex, SlotIndex, VNInfo *): Assertion `S < E && "Cannot create empty or backwards segment"' failed.
PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace.
Stack dump:
0.      Program arguments: llvm-project/build/bin/llc reduced.ll -print-after-all
1.      Running pass 'Function Pass Manager' on module 'reduced.ll'.
2.      Running pass 'RISC-V Insert VSETVLI pass' on function '@silk_resampler_down2_3'
 #0 0x0000556207b594d8 llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (llvm-project/build/bin/llc+0x21e24d8)
 #1 0x0000556207b5702e llvm::sys::RunSignalHandlers() (llvm-project/build/bin/llc+0x21e002e)
 #2 0x0000556207b59bf6 SignalHandler(int, siginfo_t*, void*) Signals.cpp:0:0
 #3 0x00007fce399d1cf0 __restore_rt (/lib64/libpthread.so.0+0x12cf0)
 #4 0x00007fce38451acf raise (/lib64/libc.so.6+0x4eacf)
 #5 0x00007fce38424ea5 abort (/lib64/libc.so.6+0x21ea5)
 #6 0x00007fce38424d79 _nl_load_domain.cold.0 (/lib64/libc.so.6+0x21d79)
 #7 0x00007fce3844a426 (/lib64/libc.so.6+0x47426)
 #8 0x00005562063189cf (llvm-project/build/bin/llc+0x9a19cf)
 #9 0x0000556206c7fb7b llvm::MachineFunctionPass::runOnFunction(llvm::Function&) (llvm-project/build/bin/llc+0x1308b7b)
#10 0x00005562071fd555 llvm::FPPassManager::runOnFunction(llvm::Function&) (llvm-project/build/bin/llc+0x1886555)
#11 0x0000556207205292 llvm::FPPassManager::runOnModule(llvm::Module&) (llvm-project/build/bin/llc+0x188e292)
#12 0x00005562071fdda1 llvm::legacy::PassManagerImpl::run(llvm::Module&) (llvm-project/build/bin/llc+0x1886da1)
#13 0x00005562061e4c85 compileModule(char**, llvm::LLVMContext&) llc.cpp:0:0
#14 0x00005562061e228d main (llvm-project/build/bin/llc+0x86b28d)
#15 0x00007fce3843dd85 __libc_start_main (/lib64/libc.so.6+0x3ad85)
#16 0x00005562061de4de _start (llvm-project/build/bin/llc+0x8674de)
Aborted
```


```
target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
target triple = "riscv64-unknown-linux-gnu"

define void @silk_resampler_down2_3(ptr %0) #0 {
entry:
  br label %vector.body

vector.body: ; preds = %vector.body, %entry
  %evl.based.iv = phi i64 [ 0, %entry ], [ %2, %vector.body ]
  %vector.recur = phi <vscale x 2 x i32> [ zeroinitializer, %entry ], [ %3, %vector.body ]
  %1 = call i32 @llvm.experimental.get.vector.length.i64(i64 %evl.based.iv, i32 1, i1 true)
 %2 = zext i32 %1 to i64
  %wide.masked.load = call <vscale x 6 x i32> @llvm.vp.load.nxv6i32.p0(ptr null, <vscale x 6 x i1> zeroinitializer, i32 0)
  %deinterleaved.results = call { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.vector.deinterleave3.nxv6i32(<vscale x 6 x i32> %wide.masked.load)
  %3 = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } %deinterleaved.results, 1
  %vp.cast65 = call <vscale x 2 x i16> @llvm.vp.trunc.nxv2i16.nxv2i32(<vscale x 2 x i32> %vector.recur, <vscale x 2 x i1> zeroinitializer, i32 0)
  %interleaved.vec = call <vscale x 4 x i16> @llvm.vector.interleave2.nxv4i16(<vscale x 2 x i16> %vp.cast65, <vscale x 2 x i16> zeroinitializer)
  call void @llvm.vp.store.nxv4i16.p0(<vscale x 4 x i16> %interleaved.vec, ptr null, <vscale x 4 x i1> splat (i1 true), i32 0)
  %4 = icmp eq i32 %1, 0
  br i1 %4, label %while.body5, label %vector.body

while.body5: ; preds = %while.body5, %vector.body
  %5 = bitcast <vscale x 2 x i32> %3 to <vscale x 4 x i16>
  %cond52 = extractelement <vscale x 4 x i16> %5, i64 0
  store i16 %cond52, ptr %0, align 2
  br label %while.body5
}

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
declare i32 @llvm.experimental.get.vector.length.i64(i64, i32 immarg, i1 immarg) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)
declare <vscale x 6 x i32> @llvm.vp.load.nxv6i32.p0(ptr nocapture, <vscale x 6 x i1>, i32) #2

declare { <vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i32> } @llvm.vector.deinterleave3.nxv6i32(<vscale x 6 x i32>)

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
declare <vscale x 2 x i16> @llvm.vp.trunc.nxv2i16.nxv2i32(<vscale x 2 x i32>, <vscale x 2 x i1>, i32) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
declare <vscale x 4 x i16> @llvm.vector.interleave2.nxv4i16(<vscale x 2 x i16>, <vscale x 2 x i16>) #1

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
declare void @llvm.vp.store.nxv4i16.p0(<vscale x 4 x i16>, ptr nocapture, <vscale x 4 x i1>, i32) #3

; uselistorder directives
uselistorder i64 0, { 0, 2, 1 }
uselistorder i1 true, { 1, 0 }

attributes #0 = { "target-cpu"="sifive-p670" "target-features"="+64bit,+a,+c,+d,+experimental,+f,+m,+relax,+unaligned-scalar-mem,+unaligned-vector-mem,+v,+xsifivecdiscarddlone,+xsifivecflushdlone,+za64rs,+zaamo,+zalrsc,+zba,+zbb,+zbs,+zca,+zcd,+zfhmin,+zic64b,+zicbom,+zicbop,+zicboz,+ziccamoa,+ziccif,+zicclsm,+ziccrse,+zicsr,+zifencei,+zihintntl,+zihintpause,+zihpm,+zmmul,+zvbb,+zvbc,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvkb,+zvkg,+zvkn,+zvknc,+zvkned,+zvkng,+zvknhb,+zvks,+zvksc,+zvksed,+zvksg,+zvksh,+zvkt,+zvl128b,+zvl32b,+zvl64b,-b,-e,-experimental-p,-experimental-smctr" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
attributes #2 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }
attributes #3 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) }
```

I think is relate to 

https://github.com/llvm/llvm-project/blob/e2f86b5584959ec2b000d183841c8fb7c3402388/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp#L1708

The `beginIndex()` value could less than `MISlot`. 

This bug could be solved by replacing those statements with

```
LIS->removeInterval(DefReg);
LIS->createAndComputeVirtRegInterval(DefReg);
```


</pre>
<img width="1" height="1" alt="" src="http://email.email.llvm.org/o/eJzMWUtz274R_zTwBSMNCD518EGW49YzSZuJM7l6QGApoQZBFgDlx6fvACRFSpbSJP-k04wjLl67v13sAySYtXKrAa5ReoPS2yvWuV1jrm_g0_aqbMTr9dcdYDCmMbgGa9kWEFmjjAx_ZK0UR_EaK7WvF61p_gXcIXrnm4jeSc1VJ2Dq2DQC_gYa0buPcg_32oHZM7XcoXgd5XRkhOI1itd-xhemt9A3H2Bbg3bHDVo8qMbdawEviG7wUePbP-511WBE14iuPOu1tWCcbDRGGXnAKN7gDxjRDNEMI0o3TOvGYW6AOcBQt-4VNwaXjD89MyMstqNQimiOKyYViCUi688fP6wfPmDblbV0mOGy22IDbWMcdg3eOddaj5reIXq3lW7XlUve1JNRTmwnre3AInqHmRZ4MCF2O8DcMLsLgJxhHLzsB8f4ExZd3XoRZE2WOPz7bJqtYTVmZtt50PbMJpWdVMI_pQ4oODYgOg5iqRRetEZqt2CVA7NgSiGyjgbeXzqtpd7illmLEc3vOs2DWT_7jk9Msy0Yb6JG47oRnQI_a-KNaO6h0wvsvtw_bBbf8L32u4W_PXz4-u3jfRgdeFajPERzlBAr1dOjAcvqVoF5FM2zpo-xHyNrjGhMMHkhhJA0zSjJy3SViGLmZvbV9sRnr3Cw51dvXUSLaZJhz4-NdQZYHRxmg6V3hBUeZn3PqojekBcaAU1E4T2xRxWdoMoJhXOovnT6QW41U39nWigwFtHiJwUTQmESTE_NUVYZPhKBaBG022Art1JXzaMLQbTB-0aKPp6GFXbJW-95JPzvBcSDgLziEK9WIuIVwY9-h1xj4NE4HFS4U7LMkv7Zup0BJpa2WZKAOqK8IhPmZM6ySNKI8QobJi2858U9lyxwSYDxauKSHnOhCbAUs7I5h2jGhUbA0olLdspF5Cv8qNWjaph4FE3NpF7yRokl-S9sRb6a2ObHbBOWhKz0HeXyxHviuL6Yb2sWR8WKVz_sJCsWreaWWh0x43lV5uXMOT8xvpMaxrj3YT-ESaf_qcfuowCaOrOf8d4oJkWZlz0yHzXHwRxVIk3TGbK7zx7MmIL-EKaiyNI0nTAdhzIlKV3RH8D0KaTGI0Rj18_iAbqiEx56aiPBohkeBVvGX4ecNyG7r1t1QPdbUGWCRROq-MinIkh4kWLe1K1UcDAF3zETEkxIN7OzwMdvnzaNdvDiBhxK8ZPc44UkJ0IoLQT2EfnDuIuspIWYYJ8kjViIIsWPjz4WH61jxj2O7C9GasxEMXOX7BijgEQA7nn9BMo8EUNSX_sMBuLkXDb8zXocM1twWDDHFHttOodRfOsPPrDwVoaFN2aWhJ-FPBARLfzpjBYLHdO-78H3UTrxdEa2vsr3_Iy0fJ8li04_6eZZL5TU3ctiq7t-DSJrAZXUEMoJ_k4FL1pnMKIp6R0vJhjlN4isQTvz2p93MC4NVqwE5SfugbvGLP3BtRc074jXGMU3uDUg7AD1aAHd-J6et2fsG3u1LJkFsZT7sKTdSSyzBKP0BpP5CozS29BOb3wfHcZm_MOMge_QbYB35sAXxZu95UwBfsEUv2Dpzf0hcHwD00gtnWRKvvkCfVFw_H3BUZDGmVKevbe9d7clvLRgpD8nMrXcglsOyxXordstvTPQIuh9bJNwEIopjgIRYWe66aSR0iDsDV5cL8yLd4233wjnWQpY1sw--XNhw8SEbm6MbGaMAfC-DfOX-mWfyZguWzJ4i-78-XLzfn3kl5-xo0c2njQ8JAHSv5UoYHsQSwO2U87OcOU3FzbqVOqPjGCU30469TafA4hHBX16uWCR91acaRMH5PDi3xfcnqkO_ogGF8zml0UHn2-XnFmXpec3ObCMspNNdqbT3BuByijrn--MQY-MMQ-ts7B_1BHm-uyBn0ednEHdA5iWU4878bPO4B7WzsxzHnR2FnUPNqAac-louXDYHiX38XEJ-DtdPYRLwZQcbGhbxULFmgX-GTsmwXKS1y2Gfx8SgZ9JxvwtozAxlPwxlT_vpIKQv9Kj_ncpfj7xXIo_YfSORQDZO2Upnd-Di67u48k1FxxgZMUbLYbUN8QdKPCp9aLj0DQg8_m1N0nYOz888Ru3pK-GG8yU3GpM31XAubZkjfLb4RwQ3-DDa_raORO-B-jGu07J-BPWTWUAsG7sq-ZYN51-llrgZ6mUAdcZjWuoG_OKaKEbPSR5AVwxj_QXSsnoKrKumdkO9WNshGof_X7ozGxr8Icd7F83j5X45YrTcNa6zsDFsjOoOqh1OAINYv_PCspwTv3TLvO7U__FVH9s_D_gU9_X7fcUiMs14X8RK89GuhMVf7naHErLpahJzm9cPCnYWVDSCxRgsJAGuJN7sIisj0b6dOq558NZPSTRCPdJ8XjuWMH62X11wofsyZwzsuwc2OEtxFcWH7eU9i9AC96Gl5v4FlFqZSX3sGiznCBKZ5MqYF5je5iJ6E2WlNIhukH0hvUP3j9E_5in076n6h91_zCg2EtPdjoUBRALb0tmFn77TkZ635tG9v3jpcfMhbScGSFU8On5SKU6u5v1v7EsMXakWd2MpDJ20OCtZCNRjsS4go9DfNDzrdrV_g030JJnSXmgy6ae0e2MfjvQnNUNm1qymmhlp-XcWDg0rBnJCjQHObZ2Ujvt1LzZsm5auGtHhnXdjdP2Bx335aj_HmJazeiXA50lYkZXM_ow5-nA72l7oPRE8YkEMdGzubuJg52oaZ2drbPTOrs7kG6kVESLAzcV04nuN2oRfiD8zBx20b7rsTV3JoRFCK7jyIoOkfWXUvFZ3vQv8n53dDgrJf5tUsakO2ah408799jtpH7C0mKfARyEc2kY-un7plI1JaJ3QKsiK9O0SFbpCjgtCSEiKuIiiXhRlTmPE0LjopjxkX7d15DcEL37cv-w-TY--9ub4fImfKij8ccoJ0UP8usOMMpICVuphwu7cDeSEdy_pfKmUwIrsBa7HQs3dp_uH1TjUEaWeGQibbhs6yeXgG2j9iBw-YoNtIpxqbfY7RoL2Drmwinc4mfpdu-_jn28f1ig-IOBupkuJhEtbqH6Attwg3gzTesvCddabJq67Rx8k8Z9ge3ldSf7dyWuY7GKV-wKrqM8KVKSpHF2tbsGEERESSZYXPFVXiUpySlhJIpJkRe5uJLXlNCUpHRF8oRG2TIuIOYkY1RUhFVFghICNZNqGWpzY7ZX4ULxOkqiFcmvwpuCDde9lJbdNpShjacZfwItULzuL-D8QHp7Za6Du5Td1vp6L62zE2cnnQpXx_3ep7dH13X9fSVYLLreP3_qjrW_db7qjLr-9SvUQen9Nf1PAAAA__-lk1zs">