<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/140590>140590</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            [SPIRV] Lowering of `select` for floats causes verifier errors
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            new issue
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          kmpeng
      </td>
    </tr>
</table>

<pre>
    When compiling the following LLVM IR targeting SPIR-V:
``` llvm
define noundef float @faceforward_no_instcombine_float(i1 noundef %a, float noundef %b, float noundef %c) {
entry:
  %select = select i1 %a, float %b, float %c
 } 
```
We emit invalid machine code due to incorrect register types in the `OpSelectSISCond` instruction:
```
*** Bad machine code: Illegal virtual register for instruction ***
- function: faceforward_no_instcombine_float
- basic block: %bb.1 entry (0x560fe0f01b98)
- instruction: %7:iid = OpSelectSISCond %4:type, %0:iid, %1:fid, %2:fid
- operand 3:   %1:fid
Expected a iID register, but got a fID register

*** Bad machine code: Illegal virtual register for instruction ***
- function:    faceforward_no_instcombine_float
- basic block: %bb.1 entry (0x560fe0f01b98)
- instruction: %7:iid = OpSelectSISCond %4:type, %0:iid, %1:fid, %2:fid
- operand 4:   %2:fid
Expected a iID register, but got a fID register
```
</pre>
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