<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/139284>139284</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            [SPARC] Disassembler doesn't sign extend and aligns PC relative disponents.
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            new issue
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          Rot127
      </td>
    </tr>
</table>

<pre>
    According to the SparcV9 ISA the branch instructions with the format 2-4 have displacement immediate values which get sign extended:


But the operand types for these displacement immediates never define a decoding method:

https://github.com/llvm/llvm-project/blob/865fb9c1a50f8b836a8c9ee6f4d1cbe7cce59fc3/llvm/lib/Target/Sparc/SparcInstrInfo.td#L224-L230

This leads to the bits being simply extracted and added as unsigned immediate operand to the `MCInst`.

The resulting branch instructions are not aligned, PC-relative or correctly sign extended values in the disassembler.

```c
echo "0x10, 0xbf, 0xff, 0xff" | llvm-mc --triple=sparcv9 --disassemble
        .text
        ba 4194303 // = 0x3FFFFF but should be 0xffffffff_fffffff0
```
</pre>
<img width="1" height="1" alt="" src="http://email.email.llvm.org/o/eJyUVE2L4zgQ_TXypXCQ5e-DD-mEQMMsNNPDXhd9lGMtshUkOZ38-0VyZyYNuwsjBKVEuF69ek_FvdfnBXEg9Qupjxlfw2Td8N2GgrWZsOo-7KW0TunlDMFCmBDeL9zJP3t4fd-n38LxRU6gFx_cKoO2i4cPHaZ0OVo38wAsr2DiVwSl_cVwiTMuAfQ8o9I8IFy5WdHDx6TlBGcMEMsCvAVcFCpS7glNmxWkfnmd-RlJfSSsm0K4-HjNToSdzjpMq9hJOxN2Wj26nIfA5RTBPGEn7j2mA5M1R6a6fMS6zateNHnXll1Oa6ybjkpBWySs30Bf1pCo2As6vigI9wv6SCz-6_-LkocFr-hA4agXBA4KpU1tnDFM9hen_6FgzPUR8ouzf6MMhJ2EsYKwU9fUo-hlwWs6dqIrG97JHrEZK1VIga2UWPejLJ_y6PjdD-7OGPMkHR_xNar3uox2FxRh5TfGqvwbK-lW449JezDIlX-YQOjgQWDk4_V8MfcoluMyoILYJK5UPHlYl-Qw9ST2z0ZuqUhD_zhEfNLQ3QMPwaFfTYgA_2Yw7hAWG4CblJ2wA7wdcoeGB31FsA6kdQ5lMPevXnpYTS8JXGkfXTELg-4TnDR025LQPcrJAmGM3goaQehNjFscnyID0h4g6TRLyPPg9MUgKY8-9vbaQ54_ASWYfhfwFraj4FAVfVXSEjYXACmPQG_lKS4QawA_2dUoEJgQt_XXZ6TPRWdqKFVf9jzDoWirpqNtWxfZNFRd10peVLKnqmpFzeqWlg0vBcdRsEZmemCU1bSmfdEwVhY72fK2oFKqURZK4UgqijPXZheJ7qw7Z9r7FYei7FlXZYYLND5NEsYW_IB0SxiLg8UNqTtiPXtSUaN98L_SBB1MGkHvb_vvB1If4fgkCyiLfiGs_TIVNpdF9T28HeCn8vE12iU--F22OjP89vNKVcch8UnrOrB_AgAA__84hayU">