<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/137736>137736</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            [RISCV] `clang` permits invalid operand for `Zclsd` instructions in inline assembly when using any optimization level other than `-O0`
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          thebigclub
      </td>
    </tr>
</table>

<pre>
    The `Zclsd` [extension](https://github.com/riscv/riscv-isa-manual/blob/main/src/zilsd.adoc) requires the use of registers in the range of `x8-15` for `c.ld` and `c.sd` instructions. `clang` will use an invalid register when the compiler is free to choose the destination. This occurs for both the `I` and `E` base ISAs:

```bash
$ cat << EOF > test.c
#include <stdint.h>

int fn(void *arg1, int arg2, int arg3, int arg4, int arg5) {
        uint64_t val;

 asm volatile ("c.ld %0, 0(%1)"
                      : "=R" (val)
 : "r" (arg1)
        );

        return val + arg2 + arg3 + arg4 + arg5;
}
EOF
$ for isa in i e; do for level in 0 1 2 3 s z; do (set -x; clang -march=rv32"$isa"_zclsd -O"$level" -c test.c); echo Return value: $?; done; done
+ clang -march=rv32i_zclsd -O0 -c test.c
Return value: 0
+ clang -march=rv32i_zclsd -O1 -c test.c
test.c:6:23: error: invalid operand for instruction
    6 | asm volatile ("c.ld %0, 0(%1)"
      |                       ^
<inline asm>:1:7: note: instantiated into assembly here
    1 |         c.ld a6, 0(a0)
      |              ^
1 error generated.
Return value: 1
+ clang -march=rv32i_zclsd -O2 -c test.c
test.c:6:23: error: invalid operand for instruction
    6 |         asm volatile ("c.ld %0, 0(%1)"
      | ^
<inline asm>:1:7: note: instantiated into assembly here
 1 |         c.ld a6, 0(a0)
      |              ^
1 error generated.
Return value: 1
+ clang -march=rv32i_zclsd -O3 -c test.c
test.c:6:23: error: invalid operand for instruction
    6 | asm volatile ("c.ld %0, 0(%1)"
      |                       ^
<inline asm>:1:7: note: instantiated into assembly here
    1 |         c.ld a6, 0(a0)
      |              ^
1 error generated.
Return value: 1
+ clang -march=rv32i_zclsd -Os -c test.c
test.c:6:23: error: invalid operand for instruction
    6 |         asm volatile ("c.ld %0, 0(%1)"
      | ^
<inline asm>:1:7: note: instantiated into assembly here
 1 |         c.ld a6, 0(a0)
      |              ^
1 error generated.
Return value: 1
+ clang -march=rv32i_zclsd -Oz -c test.c
test.c:6:23: error: invalid operand for instruction
    6 | asm volatile ("c.ld %0, 0(%1)"
      |                       ^
<inline asm>:1:7: note: instantiated into assembly here
    1 |         c.ld a6, 0(a0)
      |              ^
1 error generated.
Return value: 1
+ clang -march=rv32e_zclsd -O0 -c test.c
Return value: 0
+ clang -march=rv32e_zclsd -O1 -c test.c
test.c:6:23: error: invalid operand for instruction
    6 | asm volatile ("c.ld %0, 0(%1)"
      | ^
<inline asm>:1:7: note: instantiated into assembly here
    1 | c.ld t1, 0(a0)
      |              ^
1 error generated.
Return value: 1
+ clang -march=rv32e_zclsd -O2 -c test.c
test.c:6:23: error: invalid operand for instruction
    6 |         asm volatile ("c.ld %0, 0(%1)"
 |                       ^
<inline asm>:1:7: note: instantiated into assembly here
    1 |         c.ld t1, 0(a0)
      |              ^
1 error generated.
Return value: 1
+ clang -march=rv32e_zclsd -O3 -c test.c
test.c:6:23: error: invalid operand for instruction
    6 | asm volatile ("c.ld %0, 0(%1)"
      |                       ^
<inline asm>:1:7: note: instantiated into assembly here
    1 |         c.ld t1, 0(a0)
      |              ^
1 error generated.
Return value: 1
+ clang -march=rv32e_zclsd -Os -c test.c
test.c:6:23: error: invalid operand for instruction
    6 |         asm volatile ("c.ld %0, 0(%1)"
      | ^
<inline asm>:1:7: note: instantiated into assembly here
 1 |         c.ld t1, 0(a0)
      |              ^
1 error generated.
Return value: 1
+ clang -march=rv32e_zclsd -Oz -c test.c
test.c:6:23: error: invalid operand for instruction
    6 | asm volatile ("c.ld %0, 0(%1)"
      |                       ^
<inline asm>:1:7: note: instantiated into assembly here
    1 |         c.ld t1, 0(a0)
      |              ^
1 error generated.
Return value: 1
$ clang -v
clang version 21.0.0git (https://github.com/llvm/llvm-project.git 913dcf1aa36f3ea2d67a0d2b05b9d1375987e553)
Target: riscv32-unknown-unknown-elf
```
</pre>
<img width="1" height="1" alt="" src="http://email.email.llvm.org/o/eJzsWE-P27gO_zTMhYghS_4TH3LI_AnQ0wBt8Q7vUsg2Y-s9RZonyWk7n_5BsjPN7HYX3e12U2DHCCBKjMgf-SMhgNJ7NRiiLZQ3UN6t5BRG67ZhpFYNnZ7aVWv7z9v3IyFU7N-d9j1UDKG8oU-BjFfWQHkHfDOG8OhB7IDvge8HFcapzTp7BL53ynen87pWXq6P0kxSA9-32rbA90epDPC9dx3w_ZPSvs9kbzvgDTr636QceQwj4eQJ7QEdDcoHch6VSedOmiFpoGKfNuu8jBgP1sV9l-kEWZp-3s4RKOODm7qgrPFZUmhphqj5qLROnqRBZU5Sq_7ZI34caXbZ2eOj0uRQeTw4IgwWu9FaT0ndkw_KyGg-w_ej8mi7bnI-oWptGNO_oGJvLrDdR7mVnvDNu11KJku_is2_Vvox7nmBnQwI4hbELd4_7BHEPQbyIeuSXijT6amn-BcfemVCNoK4n80pE_BggG9OVvUIfCfdkAO_xaiQbuAXsriQiwu5jNRAfQNsh8s3KROq4kPAk9QgbmZfKP0RT1bLoDQh8A1wHglB4CWL9lg6K3PgDXB-Ye7lB2KHUS_u3gLn0VD0wpt4YdG5RTFH01yYirtnQMvnKEzORKwI_CaFfRbEWSjOQrlcr--A7e4f9gsHkUrlZSxChQTiBnubDjWdSMdjhjlyFOjxaVED33gKuP4U96nkcH2UrhtB3LmT4DFIXigvgfMPT7HdcP0wHyarMch1d-Y6BYbUjRbfPgc00ZyRAsR-9mroeY3Iv-pYPXtjFw7Y7pd22beYyF-YWASxq0DsuIhWyDnronBuMPtILnZByumX1lwYqxDq2z9bS_Hqb1RVmVpC3CqjlaHoIHaJ2OUgdnWEZ2ygGaYP0gQlA_WxByxK7-nY6s84kqPFV_7CV8ImqzMyyS6r8legZiz5nBkcyJCLzrKvUJB_CwX8h1Bw_r6Dir806T9TxsVr0V-bAv9a9H9zxp9ei_46FND3v9f0877XP4av5D3kV-LpZ3uRr9otV2Ph9ZW-OgX_2Ff6ahl_faV_PAXFmYITsN0snsh5ZQ3yPGMZG1TA3x-UaX06L-tHZ_9DXcjirSYXfXfIpRTVQZDkfVVL1vOWlW3T56Ium01NZSnmgN5LN1CIwNLATfD1ZP5r7EfzvJI-XI6VVv1W9I1o5Iq2eV2Um02R5_Vq3MquFKIpDlUt8qZqqe-pFXV7EGLDaFMVK7XljJes4Bsuio2oM37Iec4PvZRdXjcNh4LRUSqdxZgy64aV8n6ibS7qWlQrLVvS_jx7dNsUeTsNHgqmlQ_-y72ggk5Tyrdv3t3-C8q7FzO7R3JHFfxXy_dybnk59Utzm3OhLcWTxnuTV2ZAaT6jfQzqqJ7SGG-Z6tgwksMwShMNrx9SAient3-MV-D7lAkPfL8k47Tl_w8AAP__cDsjcw">