<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/136087>136087</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            [RISCV] Missing register overlap check for XTheadMemPair loads
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            good first issue,
            backend:RISC-V
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          topperc
      </td>
    </tr>
</table>

<pre>
    The XTheadMemPair extension requires rs1 != rd1 && rs1 != rd2 && rd1 != rd2. We don't check for this in the assembler today, but binutils does.

We need to add a check to validateInstruction in RISCVAsmParser.cpp
</pre>
<img width="1" height="1" alt="" src="http://email.email.llvm.org/o/eJxUkU1r3DAQhn_N-DLE2OPPPfiwzbKQQyC0IelVtmZtNbLlasZL8--Ll9AmJ4lX4v3gMSJuXJg7qL5BdUrMplOInYZ15TgkfbDv3fPE-PN5YmMfeX4yLiL_UV7EhQUj_95cZMEoOQLlUJww2v1aA9VfVfqn2s9qiq-MNixAjeIw8fCGlxBRJyfoFtSJ0Yjw3HuOqMGad6B77DfF3i2bOi9oA0sK2RGy4yvjwmxRAxpr0Xw4asCr8c4a5YdFNG6D7vXdgt8ffty_HGV-MlE4psO6JrYr7KE4mIS7vCnLtqGsLpOpMwVTm1d1UbZtbXuq84s5tIfBHobmUuZV4jrKqMrKvMnqMs_KtCpsc6mpKfO66XNbQ5nxbJxPvb_OaYhj4kQ27vKiztom8aZnLzcWRGMIFi8uiuLtExAB3QNRb4Y3XiwUx7373cv-UJ2S2O2md_02CpSZd6LyP0ad-hvk21yoTvjoRNwyYuTRiXLEcOXozfoJwVfoPhgryRZ9N6muAsUR6Ax0Hp1OW58OYQY674Efx90awy8eFOh86y9A54-d147-BgAA__98zMmB">