<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/135997>135997</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            need help on the code in RegAllocGreedy.cpp->tryAssign()
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          BaoshanPang
      </td>
    </tr>
</table>

<pre>
    I am trying to understand this part of code:

```
568 │ // If we missed a simple hint, try to cheaply evict interference from the
  569 │ // preferred register.
  570 │ if (Register Hint = MRI->getSimpleHint(VirtReg.reg()))
  571 │ │ if (Order.isHint(Hint)) {
  572 │ │ │ MCRegister PhysHint = Hint.asMCReg();

```

The 'Hint' is always 'virtual register' as when it is set by setSimpleHint it's type is forced to be 'virtual':
```
847 │ Register getSimpleHint(Register VReg) const {
  848 │ │ assert(VReg.isVirtual());
  849 │ │ std::pair<unsigned, Register> Hint = getRegAllocationHint(VReg);
  850 │ │ return Hint.first ? Register() : Hint.second;
  851 │ }
```
But the function "Order.isHint" would only return true when 'Hint' is phsical register:
```
 113 │ /// Return true if Reg is a preferred physical register.
  114 │ bool isHint(Register Reg) const {
  115 │ │ assert(!Reg.isPhysical() ||
  116 │ │ │ │ │ │Reg.id() <
  117 │ │ │ │ │ │ │ │static_cast<uint32_t>(std::numeric_limits<MCPhysReg>::max()));
  118 │ │ return Reg.isPhysical() && is_contained(Hints, Reg.id());
  119 │ }

```
 
How this code can works? isn't the code dead actually?
</pre>
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