<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/135639>135639</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            [GreedyRegAlloc] Multiple spill reloads into same register without intermediate def/overwrite
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            llvm:regalloc
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          JanekvO
      </td>
    </tr>
</table>

<pre>
    llvm-project git hash: `c9eebc7af440dc012c94d25351eaba92e6a57910`
command: `llc --mtriple=aarch64 aarch64_reprod.ll`

Reproducible provided for aarch64, but am seeing it for amdgpu as well (I assume it can happen for any target using greedy).

>From the AArch64 reproducible provided (`aarch64_reprod.s`):
```
...
fmov    d16, d19
fmul    d7, d6, d7
ldr d6, [sp, #40]                   // 8-byte Folded Reload
fnmul   d13, d1, d18
fmul    d24, d3, d24
fmul    d11, d30, d22
mul     w11, w1, w11
fmadd d26, d9, d22, d26
fmul    d17, d8, d17
cmp     w8, #3
fmadd   d31, d6, d18, d15
fmul    d27, d27, d28
ldr     d6, [sp, #40]                   // 8-byte Folded Reload
fmadd   d9, d0, d18, d14
fmul    d8, d4, d23
...
```

Where offset `#40` is reloaded multiple times from the stack into `d6`. Between the 2 reloads, a use exists as `fmadd   d31, d6, d18, d15` but no defs for `d6` that would overwrite the initial reload. Looking into it, it seems to be an unfortunate split+spill combination (albeit, the split in the aarch64 example is particularly confusing. The amdgpu case I've been looking at shows a more direct `split->spill->superfluous stack reload` combination.) where `spillAroundUses` will indiscriminately reload for all uses within an interval regardless of whether a previous reload is (or could be) still live. Within the `aarch64_reprod_regalloc.txt` dumps the virtregs in question are `%170` and `%171`.

I'm personally not too familiar with greedy regalloc details so I'm not sure how easy a fix will be but it seems that regalloc changes are (understandably) under a bit more scrutiny so I'm not convinced that it'll be a trivial fix but I'd like to hear from the people more familiar with the greedy regalloc, if possible. Perhaps there is some low hanging fruit I'm overlooking.

[aarch64_reprod_regalloc.txt](https://github.com/user-attachments/files/19739025/aarch64_reprod_regalloc.txt)
[aarch64_reprod.ll.txt](https://github.com/user-attachments/files/19739078/aarch64_reprod.ll.txt)
[aarch64_reprod.s.txt](https://github.com/user-attachments/files/19739079/aarch64_reprod.s.txt)

</pre>
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