<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/135411>135411</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            [InstCombine] Missed shl + add + and optimization
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            llvm:instcombine,
            missed-optimization
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          nikic
      </td>
    </tr>
</table>

<pre>
    https://alive2.llvm.org/ce/z/4m2gVM
```llvm
define i64 @src(i64 %a) {
  %shl = shl i64 %a, 5
  %add = add i64 %shl, 47
  %and = and i64 %add, -32
  ret i64 %and
}

define i64 @tgt(i64 %a) {
  %and = add i64 %a, 1
  %shl = shl i64 %and, 5
  ret i64 %shl
}
```
</pre>
<img width="1" height="1" alt="" src="http://email.email.llvm.org/o/eJx8kk-P2yAQxT_N-GIlggFMfPAhf2Sph732joHYtBhHhkTqfvoKNuusVmoly0-IH8x7w6gY3Ris7UCcQFwqdU_TsnbB_Xa6Ghbzp5tSukVgR8AesFfePSzuvX_M-2UdAXttAft3wJ7POP58A3KEhnx8mQJyNPbqgq1dw2vgJK4a8FAWKBRgW4M8ATnWeR0nXwO71FlfyLkWn4AypgBZn0CcfEa43JjwZMLGKGMys2NYoNWmbSeYbFle8v-71zSmf3vdyrysFK_0f2GCecX54iJn2Fx8tq8yHTMta1VlOyo5Zy2nB1pNHWohh5a3jWRskNemIUYp5FJy3VwPwlauQ4KCcEqpFA3SPdPM6HbgWvPDlRgJnNhZOb89ZOVivNuOMsEprbwarI9lJhDLK7KjCzHpZR5csIAIeAbE2cVozW65JTe7d5XcEvKeuFRrl4_thvsYgRPvYoqvWsklXybuR4jp_LxTXOq3cl3pF-CpNLZoMPXXEtV99d_GcnRpug97vcyAfTH8IbvbuvyyOgH2JWAE7J8ZHx3-DQAA___IBdox">