<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/133429>133429</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            [llvm-mca] Add instruction customization
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            new issue
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          r-belenov
      </td>
    </tr>
</table>

<pre>
    I'd like to get feedback on the idea of customizing properties of individual instruction (using custom private InstrDesc and callback in InstrBuilder::createInstruction). Most obvious use is to model cache misses by manual annotations in the input assembler code, but it also opens the door for "what-if" analysis during CPU design (thus generic customization seems better than just specifying the latency). I have internal implementation; primary idea is here - https://squidex.jugru.team/api/assets/srm/40f77a92-171d-425b-8174-8b306afb22fe/llvm-upside-down-cppconf2025.pdf - on slide 49 (slides in Russian, but the code should be clear). Still need to get approval to contribute  the code from the employer, but first would like to know whether it may fit well in MCA code base.


</pre>
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