<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/133048>133048</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            [CodeGen][ARM] Missed optimizated load store pair instruction combine
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            backend:ARM,
            llvm:optimizations,
            missed-optimization
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          hstk30-hw
      </td>
    </tr>
</table>

<pre>
    https://godbolt.org/z/db17KEWK1

```
typedef struct tagContext {
    unsigned long long int a;
    unsigned long long int b;
    unsigned long long int c;
} Context ;



void test(Context *context) {
    context->a = 0;
    context->b = 0;
    context->c = 0;
}
```

GCC output:

```
test:
        movs    r2, #0
        movs r3, #0
        strd    r2, [r0]
        strd    r2, [r0, #8]
 strd    r2, [r0, #16]
        bx      lr
```

llvm output:

```
test:
        mov     r1, #0
        str     r1, [r0]
 str     r1, [r0, #4]
        str     r1, [r0, #8]
        str     r1, [r0, #12]
        str     r1, [r0, #16]
        str     r1, [r0, #20]
 bx      lr
```

ARMLoadStoreOptimizer Pass have Pre/post register allocation
</pre>
<img width="1" height="1" alt="" src="http://email.email.llvm.org/o/eJyUVE1vqzoQ_TXDxkpkxjgkCxYkKV30Va96b3HXBjvBt4CRbXLb_vorQ5py-32jUQb5nBnPOaARzuljp1QGfAt8H4nB18ZmtfP3jC7qX1Fp5GNWe987YDlgAVgcjSxN45fGHgGLJ8BClnF6c_XjJgaah1jRc9DcP_ZKqgNx3g6VJ14cd6bz6sETSLdAc0IIGbpxCEka0x2nP915IoB9wSi_ZFQTA9I9udw7nTzHyWhJvHIecH2hYF5Nj4Cb2aDnwwWwK0GA7Ql9GWCGlZ9g1RyDdP_KLqD59W5HzOD7wQfH3xoaRh0Bcv615uRCtgi4I4CMvgYtewdx3spZGd9aCnz_BWFqsz4TP2bEqz97lQ9TbuxbwU1zav9a8Zht_L6uOTjT9R4y1SdvlH9AXH-XGOO3mavvMvFZyGdu5v_d_mOE_N8bq_7tvW71k7LkTjhHanFS5M4qwKI3zhOrjtp5ZYloGlMJr00XyYzJDduISGVxmuAmZZskjeqMU4nrhG9KvoqrZCWVUHF1iA9CIWd8fYh0hhQ5ZbiiKfIkXaaVSFm8ideUraoyFpBQ1QrdLMP7Dssj0s4NKosZo8k6akSpGjfuIcRSVPeqk8CCHMDweQFiKASWm0nVOK-7gK12TsnFHAwY30c2C4WLcjg6SGijnXcvM3jtm3H77YxU16oLDvNtuJXvye3Yk1x6jutFSOKCuaQX2hLdTZtNm45Upi11p6LBNq9Xpvb1UC4r0wIWo4wpLXprfqrKAxajGQ6wOPtxyvB3AAAA__8HBo2D">