<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/133020>133020</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            [RISCV] Compiler crash on splat vectors with illegal types
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            new issue
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
            mshockwave
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          mshockwave
      </td>
    </tr>
</table>

<pre>
    Given the following IR:
``` llvm
target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
target triple = "riscv64-unknown-linux-gnu"

define void @foo(<3 x float> %0) #0 {
entry:
  %1 = extractelement <3 x float> %0, i64 0
 %broadcast.splatinsert = insertelement <vscale x 2 x float> zeroinitializer, float %1, i64 0
  %broadcast.splat = shufflevector <vscale x 2 x float> %broadcast.splatinsert, <vscale x 2 x float> zeroinitializer, <vscale x 2 x i32> zeroinitializer
  %interleaved.vec = tail call <vscale x 4 x float> @llvm.vector.interleave2.nxv4f32(<vscale x 2 x float> zeroinitializer, <vscale x 2 x float> %broadcast.splat)
  tail call void @llvm.vp.store.nxv4f32.p0(<vscale x 4 x float> %interleaved.vec, ptr null, <vscale x 4 x i1> splat (i1 true), i32 0)
  ret void
}

attributes #0 = { "target-features"="+64bit,+a,+c,+d,+experimental,+experimental-zicfilp,+experimental-zicfiss,+f,+m,+relax,+v,+zaamo,+zalrsc,+zba,+zbb,+zbs,+zca,+zcd,+zcmop,+zicsr,+zifencei,+zimop,+zmmul,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b,-zvl1024b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl4096b,-zvl512b,-zvl65536b,-zvl8192b" }
```
And this command:
```
llc -O3 input.ll
```
The compiler crashes during RISC-V-specific DAG combining.
</pre>
<img width="1" height="1" alt="" src="http://email.email.llvm.org/o/eJycVUuPozgQ_jXOxQKZMo_kkAPd2R7NaaWZ1dyNKYJ3jEG2odP59SvzSLoz0yvtSlHqo55fmSosnFNng3gk2RMB6Fzby5-vYkICQLLTToy-7e3xrt9Vff12_KImNNS3SJte6_5VmTP9-o3wkrCS5Gz5Ua2njrDSC3tGT2vhhRZv_egp4SdKADDqCC8xGggv83T-i9QNJLAnvExgHxkOi-570AHcc3qrBo1bPqucnPI0Gs1P07-aSCszXqKzGZcYwsoaG2WQTr2qKUlZ0_ckVHnm9EIb3QtP-B-UQMYIHCgBzigpnggr0Xj7trRHgz2ZS-LFWyE9auzQhK5-l-eZqjylLEQSyCrbi1oK52M3aOGVcWiX81jgu1yTk0IjvVB4n_SKtldGeSW0uqIN-WfbzOpDtd-Umwu5dmwajRNK39vPC31GNtT4L-wefVV4mb96roSV8Wg1ignreEI5E_ZCaSqF1h9ypR_IpiwMW7w0Fd-zQGwuU9pwWN7z_2b9L8dC4DCzv9PcxmuhNMTO9xY3IvHAHrikD_kfziDQGbylZtT6kVoIVUmIW98v7FVCvR0xsArTwIGyjaFFP3MLu1Cclo0Q3ltVjR7dOu9hlYqnsE7LjkUNCj9adGGJ-Cn8w1OeVipMAoEnsQi5iHoReBnQqjDJQv-qia5KNkoPn1mcWyzNIrpFWNTissBpEVchun6D2rqVw7USG6g2sGa8ys0k6w10_UrkqqSzG2zQSFTb092n68a1o-uEHJp3-HLDeVq_w807fPPRCeyr2wOHO87TgKPgwuCOc76_PQBL9zec5RvkUOQ3fcoON0OWwAbzLOM3_T45BAPQdRy2LzdhZWlq6lvlqOy7Tpj64dtOWKm1pNGfnCozjD7W-sH8V4shdlAaLZVWuBYdrUcbropvX78_Rz8iN6BUjZL0VH4JvpUyypzjXX3k9YEfxA6PSZHCIc3zAnbtMS9Ys2-KNKmyDEQus6IogGOdsKrei1zu1BEYZIxDBjxLEoiTQ9HsxV40DVYNpJKkDDuhdDyvZm_PO-XciMeEcwZsp0WF2q13ocFXOlvXq9AeQ1BUjWcXdls57-5pvPJ6vkRDaz9IdqLPH3qnvVlXdPlEOfqqfEuV1ngWmvq3Ad1utPrYej-4cNjwQuDlrHw7VrHsOwIv83W6iGiw_d8oPYGXmaIj8LL2MB3hnwAAAP__ojVlxQ">