<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/132787>132787</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            [RISCV] Ideas around store merging in DAGCombine
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            new issue
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          preames
      </td>
    </tr>
</table>

<pre>
    This issue is simply a collection of observations around potential future work around store merging, triggered by recent investigation around f138e36.  I don't plan to work on any of this in the near future.  

* We don't have a ROTL for pairs of i8 merged as i16, but we do have bswap followed by right shift.
* For vectors, we have vrgather.vv which can do arbitrary rearrangement of elements (at highly variable costs).  We could cost the shuffle mask.
* For very large merge sets, there's some tradeoff point where using a vector is in fact profitable. We ignored this for now, but might want to explore this refinement at some later point.
* If we ever have a calling convention with vector CSRs, we probably want to revisit this heuristic.  This intersects with some of the ideas we've talked about with internalizing during LTO.  

Not store merge related, but noted in some of the same tests:

* If we have a FP load/store pair, don't have an available FP CSR due to other register pressure, but do have an integer CSR, we could type convert.  This could be done in either direction, but would probably have to be done late in integration with the register allocator.  Note that this isn't spilling to another register class, it's entirely changing the type so that we don't have to do a cross class copy.  
</pre>
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