<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/132685>132685</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            MIPS/ASM: may optimize SW + ADDIU
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          wzssyqa
      </td>
    </tr>
</table>

<pre>
    An asm code like
```
        .set    reorder
xxx:
$BB0_1: # %for.body
        sw      $4, 0($2)
        addiu   $2, $2, 4
        bne     $2, $3, $BB0_1
```

may be optimized to
```
 .set    reorder
xxx:
$BB0_1:                                 # %for.body
 addiu   $2, $2, 4
        sw      $4, -4($2)
        bne     $2, $3, $BB0_1
```

So that the `sw` can be placed into delay slot.
</pre>
<img width="1" height="1" alt="" src="http://email.email.llvm.org/o/eJyUkkGL2zAQhX_N-CJi5JGsxAcdnAbDHhYKofRYZGsSq5Wj1JI3yf764iah6bLQ7WB4l8-PefNkYnT7A5GGcg3lJjNT6sOoT68xXn6arA32ousDM3FgXbDEvPtBwGtQ_Pbxmt0mj5RmHSmMlkbg9fl8BlHPOMr1mn8rQNQMUDDAchfGfHZ_MIinqwJKCfiJccAVoETA6oEy1rrpSuFM3VU-MO2B7k53Rtz0usffCYDXg7mwllg4Jje4V7IshbcxP5jvX_NO_o9EenuchXz3Ov-ffBtY6k1iqScGiscTKM46c5jPcfSmI8vcIQVmyZsLiz6kPLNa2EpUJiNdLCWueKEKlfW6Uty0dmfKlcRlURWSuuVKVCW3XUudkJnTyLHkAiVfCiFUXu34UiqjULYtqUqC5DQY53PvX4Y8jPvMxTiRLgSqVZl505KP98c66platNM-guTexRT__Jdc8qSfnz5vAZt6-zx3M7d8r5htvzLANas3m6cv2TR63ad0jHOh2AA2e5f6qc27MAA2s-tNFscxfKcuATa_V4uAzW27F42_AgAA__8ZK-B1">