<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/132826>132826</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            [llvm-exegesis] Machine Verification error for lea with 32-bit registers operands for address
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            backend:X86,
            tools:llvm-exegesis
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
            boomanaiden154
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          boomanaiden154
      </td>
    </tr>
</table>

<pre>
    Putting the following instruction into `llvm-exegesis` through a snippets file:
```x86
        leal    -32(%eax,%eax), %eax            # encoding: [0x67,0x8d,0x44,0x00,0xe0]
```

will result in a machine verification failure.:

```
*** Bad machine code: Illegal physical register for instruction ***
- function:    func0
- basic block: %bb.0 (0x5555fa9ba8e8)
- instruction: $eax = LEA64_32r $eax, 2, $ecx, 0, $noreg
- operand 1:   $eax
$eax is not a GR64 register.

*** Bad machine code: Illegal physical register for instruction ***
- function:    func0
- basic block: %bb.0  (0x5555fa9ba8e8)
- instruction: $eax = LEA64_32r $eax, 2, $ecx, 0, $noreg
- operand 3:   $ecx
$ecx is not a GR64_NOSP register.
LLVM ERROR: Found 2 machine code errors.
```

It seems LLVM does not acknowledge that an lea instruction in 64-bit mode can accept 32-bit registers in the address argument assuming an address-size prefix (`0x67`) is added to the instruction (despite generating this code, most likely due to #122102).

Opening up this issue mainly to discuss how we should go about fixing it. The below patch works, but causes some test failures, mostly in `llvm-exegesis`.

```patch
diff --git a/llvm/lib/Target/X86/X86InstrOperands.td b/llvm/lib/Target/X86/X86InstrOperands.td
index 53a6b7c4c4c9..db1f9aa68c48 100644
--- a/llvm/lib/Target/X86/X86InstrOperands.td
+++ b/llvm/lib/Target/X86/X86InstrOperands.td
@@ -479,7 +479,7 @@ def lea64_16mem : Operand<i16> {
 
 def lea64_32mem : Operand<i32> {
   let PrintMethod = "printMemReference";
-  let MIOperandInfo = (ops GR64, i8imm, GR64_NOSP, i32imm, SEGMENT_REG);
+  let MIOperandInfo = (ops GR32_GR64, i8imm, GR32_GR64_NOSP, i32imm, SEGMENT_REG);
   let ParserMatchClass = X86MemAsmOperand;
 }
 
diff --git a/llvm/lib/Target/X86/X86RegisterInfo.td b/llvm/lib/Target/X86/X86RegisterInfo.td
index 48459b3aca50..12a60b881b09 100644
--- a/llvm/lib/Target/X86/X86RegisterInfo.td
+++ b/llvm/lib/Target/X86/X86RegisterInfo.td
@@ -849,6 +849,9 @@ def TILEPAIR : RegisterClass<"X86", [untyped], 512, (add TPAIRS)> {let Size = 16
 // Register categories.
 //
 
+def GR32_GR64 : RegisterCategory<[GR32, GR64]>;
+def GR32_GR64_NOSP : RegisterCategory<[GR32_NOSP, GR64_NOSP]>;
+
 // The TILE and VK*PAIR registers may not be "fixed", but we don't want them
 // anyway.
 def FixedRegisters : RegisterCategory<[DEBUG_REG, CONTROL_REG, CCR, FPCCR,
```

Not sure if there's a better way of doing this.
</pre>
<img width="1" height="1" alt="" src="http://email.email.llvm.org/o/eJzMV11v47oR_TXMy8AGRX1YevCD7diLoMkm8KaL-xZQ4khmI4mGSK3t_vpiKNmxs9v27n0oGiiWSHHODA8PZyhpra5axDmLl0yI3JhGtlIrbIM4YkKw-P5O9m5nuvntu7vcqNP8pXdOtxW4HUJp6tocqKVb67q-cNq0oFtngCW8rn80EzxihVZblnBwu8701Q4k2Fbv9-gslLpGFi4YX7CED9cxTajJsxplzXg2CQUTKRMxyiMTq_NDxsQKhgZc_TERAraFUbqtWLgAFi_5MZkxseLHVPlbFPkb5_6GnMX31_6988VB1zV0aPvagW5BQiOLnW4RfmCnS11IP9VS6rrvcDpO4ROKGC9YSnWxL4yiGcNDXWMla9jvTlYXkpxV2jrsoDTdDZ8XHMYXEyj71ncTBoBvcv8il1YXkNemePcTF3GeTzkwkfJjHMdxKbNcppgSdTT-ysUwPiIqWXgPj-tFEr2Fohs7iWkx0B1h4Zt8bLamw8rDmT12slUQDIGNlsSCx9UWWuNAwpdtEl3mOh1Z-79g6n9OVfhBVXGmqvhE1dvX528vN3w9Pn5_gvV2-7wl843pWwXihjTArjOdnf6s6gcHFrGx4EGUwdFV8d6aQ42qQnA76UC2UKP8tKshiSa5dtCQi0K2IIsC9w5C4bvPMVoaStlBKtWhtSC7qm-wdSCt7RvKFmQ7vJxY_U-EfYelPhL_LOF-uyaciYyYkEqhAmc84u1apwrtXjuEClvs5JiVtB2EI1bQGOug1u9Yn0D1SChMhIEQARdMZKP4nvfYkmm_H6y1tT1CI3Vbn8hEaVv01sLOHOCAYHemrxVUBmRuegelPvoE6KbwukPIsTYH2EtX7OBgundLgeS9g0L2Fi1Y0yA4tO6cO-w50vpExP0ib04_pRYPzvhC6bKEyaTSDiQTGzKjm86Z2LzKrkLHxOaPNBl-H4i750F5duoU5L9vw_hCtwqPEIcyyWdFVERFNp2qPCgzKZO0iFIIOE-iiHQ-mfyVuPw-WA7XX4yRRZxFHCbRjIrEDJhYXh6HVwpLEngSvQVJgw3QThoxWLjSQcLCNbDZkvEF0P_H-FD8YnworsYD1OjgpdOte0K3M8onCibEfuhqtlhih22BVGzDpU8J3ubpYcR8aEszWqVmb30iIJnoVDcNPVwyg-8Nxdj9bf3laf319W27_kKpy2MTjf8NPRRvv3Ax9v5JP-d5y85i90QSXdXSWu_ojzR5wmZhmwtnA7Oz-5Hg35Pydsw0NJE_qeRPJhchR2kUZ3koCxnz6TQQMuF5mgY5z35byD-7-C0d_8J8lHEakXYTkvHwmF3L-PXhcf2yeNh6TZ5BPPUsXDEhvIOhJMXLvnWnPSo68YgVxMFYqlKpFLwSyje_nl7LtJrfKDvTCgaJXymxYWJz8QKFdFiZTqOvNePrcUmZWFJ4FxndxjcYnijEeEljzqqm0ML1Rbo3EEMt_M84F7V-SPcW8WoelK-JPqBi_P1vTCw8kR-FrJEnXx9zpP1b6iOqkUvK6AcEZVomZg4OsnVUoZordNmeDvI0PaePDVlvL9D_fhb36-XfvwxbawWr56-v2-fHS3O1pdvmZXj4ucB_NQ5s3yHokuLpkImZBQk5OlqwgzyBKUGZc62c3ql5qLIwk3c4D2aRSGPOg-xuN08yNUtFPhPlDOWMlyqKM5FEoZTxDFWW3em54CLmoYhEwHkgpirMYj4rirKcRShyUig2UtdTUv7UdNWdL63zIBSpSO5qmWNtz18hsnhHSgyLi16ZEM6Y2rJwcVsRh0-Ubu57876yLOK1ts5-OHLa1f4D59Yyvoen8Zz0_foY789L_jRJp56DdrufDzXjoc36YePp5a7v6vnOuT0FOSx7pd2uz6eFaa62PAWx78w_sKAt71mwTGxGIn7Mxb8CAAD__9dnF_Q">