<table border="1" cellspacing="0" cellpadding="8">
<tr>
<th>Issue</th>
<td>
<a href=https://github.com/llvm/llvm-project/issues/131879>131879</a>
</td>
</tr>
<tr>
<th>Summary</th>
<td>
[RISCV] RVV with inline assembly
</td>
</tr>
<tr>
<th>Labels</th>
<td>
new issue
</td>
</tr>
<tr>
<th>Assignees</th>
<td>
</td>
</tr>
<tr>
<th>Reporter</th>
<td>
mp-17
</td>
</tr>
</table>
<pre>
Hello,
Is it possible to compile .c files with clang targeting `-march=rv64gcv` without letting the compiler insert any vector instructions in addition to the ones written in inline assembly?
Use case: I have plenty of code that uses inline assembly to set precise sequences of vector instructions (this is also useful for verification), and I use it with .c code.
With older versions of clang (v16), `-fno-vectorize -mllvm -scalable-vectorization=off -mllvm -riscv-v-vector-bits-min=0` did the job. Everything compiled as my RVV inline assembly was not even there, except for correct variable handling in my extended asm.
Now, with clang v20, I am not sure this is enough/correct anymore. I compiled my code with these options, but the compiled program looks messed up. After every vector instruction, I see something like this:
```
8000201c: 0c0572d7 vsetvli t0, a0, e8, m1, ta, ma
80002020: 0b358513 addi a0, a1, 0xb3
80002024: 00e54583 lbu a1, 0xe(a0)
80002028: 00b10723 sb a1, 0xe(sp)
8000202c: 00c54583 lbu a1, 0xc(a0)
80002030: 00b10623 sb a1, 0xc(sp)
80002034: 00a54583 lbu a1, 0xa(a0)
80002038: 00b10523 sb a1, 0xa(sp)
8000203c: 00854583 lbu a1, 0x8(a0)
80002040: 00b10423 sb a1, 0x8(sp)
80002044: 00654583 lbu a1, 0x6(a0)
80002048: 00b10323 sb a1, 0x6(sp)
8000204c: 00454583 lbu a1, 0x4(a0)
80002050: 00b10223 sb a1, 0x4(sp)
80002054: 00254583 lbu a1, 0x2(a0)
80002058: 00b10123 sb a1, 0x2(sp)
8000205c: 00054583 lbu a1, 0x0(a0)
```
Moreover, the program's functionality is compromised.
Thanks a lot for the help.
</pre>
<img width="1" height="1" alt="" src="http://email.email.llvm.org/o/eJx8lk93ozYUxT-NvHnHPkL8MSy8cCf1qRftYtpO10I8jGaERCVB4n76HgliZ0LinBycgO79vfv0x3Dn5EUjHkj-C8mfNnz0nbGHftgm-01tmuvhN1TKEPaF0COhx7MD6WEwzslaIXgDwvSDVAg7Aa1U6OBZ-g6E4voCntsLeqkvQAq67bkVHUmf7FRkFzGRgsaxZvSg0MdhvsNXQwtSO7QeuL7ChMKbeMfbUXhptAOpgTeNDP-EOoLU6MC30nvU4bnUSmoE7hz2tbqS9EToEQg9_u0QBHdI0iOcoeMTwqBQ-yuYFoRpEHzHPYwO3XuTwHLoYbAopENw-O-IWqAL0o_qJKz0nXQgHXDlTDBtRwWtsTChla0UPAwkrCLsC3DdwDmMCX2OrdyJWNFunoB_wi2jGoxqFwmh5thvwsopKRan0PJWm-1ck_wPYdsrNfWwdYIrXiu8PZoLSJ9M294GWenEtJ2WMdtaerftZRhFw8w1sokt_27qHfw6ob36LszgMnsNcAf9Fb5--7Zq4DN3oI0HnFAHD4uhXHwROPjYFmGsReFh4laGOqHjulHBXepgii8edRMZ_dKWP8xzMHmz9iZGw50z8D7S3GjDrM4TgdqMl46w0yuK62tvLO7gfE_QX-elEE19hw7BDHFOg3E9-rfLtYHBmovlPShjfjjo0TlsYBx2cGw92pDWfrSQ5yIdIjjT49xEJX_MtZL0OOcjBV1-6bGklDKaiLB4qaD5njV7ILSaHPpJSUIrH6PzeMUyXPskXD2Pf_ObCaPRpE7zMk9SCD-EVmFbhY_ZJSrpS53eVVlUUcyzvLypVD0G0TIcCSuDQXVXlbOqTuiepUHh6ncCN_wkmBNS8QAjVpiU3jAFu6l-QokVKl0S8QcovkbdE-WfoPgataQqZ9QKU64w2T1R9gmmXGGyJVHxIFGxRt0TpZ-gijVqSZQ9QGUrVH5PxT5YDtkKky-J2AMMW2PuiZJPErE1aklEH6DoG9Tb3Uno8Xdj0Uxo45br8PVkIGzvoB113PZcSX8NR1E4P6zppcNmOcv-6rj-4YCDMvN5GDw6VMNu0xzSpkorvsFDss9YyhjNqk13aDLEErFmTVY3Oc_bLM8KhnnNWJ6yItnIA6Msp2lSJmXQ7EohaNVWTVs1tKR5QTKKPZdqF07_nbGXjXRuxEOSJuW-2iheo3LxLYExjc8QnxLGwkuDPQTRth4vjmRUSefd3cZLr-Lrxdfzn1--kfwpfifEM_XdF8NmtOrQeT_EY4-dCDtdpO_GeidMT9gpWC4f28Ga7yg8YadYiCPstFQ6Hdj_AQAA__8a4ZWy">