<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/131601>131601</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            Auto-vectorize saturating addition
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            new issue
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          Validark
      </td>
    </tr>
</table>

<pre>
    This code ([Zig Godbolt](https://zig.godbo.lt/#z:OYLghAFBqd5QCxAYwPYBMCmBRdBLAF1QCcAaPECAMzwBtMA7AQwFtMQByARg9KtQYEAysib0QXACx8BBAKoBnTAAUAHpwAMvAFYTStJg1AAvPMFJL6yAngGVG6AMKpaAVxYM9DgDJ4GmADl3ACNMYhBJAGZSAAdUBUJbBmc3Dz04hJsBX38gllDwqItMKyyGIQImYgIU908uYtKkiqqCHMCQsIjohUrq2rSG3tb2vILugEoLVFdiZHYONAZegGpe9BWAUkiAERWAATwWOOqITYAmc/WL84ntgCFNjQBBJ%2BfMVROCFaoGNfcIDECOEtgBWe4AKk2oJ2rgAbNIVvRPCtXAljJgJqiEVsAOyPF4rIkrPBUFZQZFbc5wlaRLhYsBgbZ7DQrEhIxhbXbMlYaLGuBjETBMZAIJjBegPN7ElYANyqKyYIGxki5LKlL2lxP4xHJQOI0PuGgAdMbkdCdljNrjHJhrY4tTKiUwqY8bTy7ZECa9CcShQRZn8mBrXridm83h8vj8/gp3OdAcDlYaoTD4Yjkcq0XgMfycdbvTLSeSIJSLjS6QymbteWzdWXuTW%2BajBcLReLJV7HXKFUwAPqyzDIZX7ABqQ6IxAgkXOpBVVpr%2BwUMQMBAgfJD3fluuQszVK31hpNZsYFpDMu7AHcEHRMOTd8QT39GTzmwXuzL%2B4PkK77TyH0epozhaxpQl2vpOisD77gB4IzqaZ7gc8F5hhGEFQQIqwKCwYj0MQfZfkOI7jtYJAQAAHHO6YLnsH7EusxoJCw6DGh8wIimuhHIHOvJzuRVrnG6DroTKDFMSxbHEBxEBcTxlErPxv7uiJ9EECx4msao7HWDJA5DnOXBwnxAlCXRRJiUcElaVJOmySs5yIvxm7oUsqyYIODB9thuFhARenDgcJGThAiLUfuZlrGpjGWZp2lrt5tB4X535zhoc6SCZf4qeZUUaZJ0kJUldmIhlznIcSrnfAAnpgBBeThiW%2BVxxETmRs7zuF2WRepMX5Tp7mMPVPn4XZaX2ZlynlZBFnMbFNlrgNnmFU1/lzu1txlTK/qBuSEU1XVy0jf5SnCVNTpLggrhUFQ9AQOmc77UNjVHSlLZYDQ/joHOhp9haeDAfiDQrAAtFw1qWt2dzghoiHeuDbwcFMtCcKCvCeBwWikKgnAAFpmGsMxzHeFx0rwBCaIjUwANYgKCaXIxwkhoxTWOcLwCggGl5MY4jpBwLASBoMct5kBQEBCzEIsgMYwIClTfB0AQYQcxAwQs8EfhVFVnA8KQGvMMQVUAPLBNoE467wQtsIIRsMLQ2s86QWDBK4wCOLhHPcLwWA4UY4iO/gQrWHgg6e5jHxDq4SsW%2BQgglCztB4MEUmG84WAs8CRwx4OxDBPEmA7JgvvAInRgU1MN1MMACijngmCXkbMSMDH/CCCIYjsFIMiCIoKjqI7uizgYZemOYifBBzkBTKgQJJJ7wNGysABKJTCkoABiTCrMDfTALVKyqORcJ9giwOl64qggywyAxK4zLGAwOeo1jOfEHgWCTxAUyWBOST2AwTgXB1C8AA0YnRwgNAyIkAQAx6ixHiNAhgYD8hdCGKvYOAgWj9CAYMRov9MF9DaH4DoKCIEWEIbAvQwxqjIPGPSaYsx5gSCRijZmjtsYcBWKPFYssGBU3JLgQg7ISb0jJuXKYCBhRYHCF/UgNM6b6E4EzUgLAJAaDSujTGHD2ac1INzLQEwWEcHOGwrRbM9HiNIDnBIdhJBAA)) ([LLVM Godbolt](https://llvm.godbolt.org/#z:OYLghAFBqd5QCxAYwPYBMCmBRdBLAF1QCcAaPECAMzwBtMA7AQwFtMQByARg9KtQYEAysib0QXACx8BBAKoBnTAAUAHpwAMvAFYTStJg1C1aANxakl9ZATwDKjdAGFUtAK4sGexwBk8DTAA5DwAjTGIQAFYADlIAB1QFQjsGF3dPPQSk2wE/AOCWMIiYy0xrHIYhAiZiAjSPLy5S8pSqmoI8oNDwqNiFatr6jKb%2B9s6Cot6ASktUN2Jkdg4sGgCAanQFVAB9WlRRWjW8ADZJNYABBQ8IOIJiNYZ9plv5zAeBBjcTNeJMJnQBLQAJ5rMR4YAMNbRNYAUgATJENKQjqdYQiuFM1nsDts3AxmGx0Nt/uh7jCAOwAIRhGgAgthBMQgSAabS1msQvcDGFDvDIgAVBCMOGs1mC4UsunsvkAOgUxFQTBlGgAzMrybCVQARNZxBB4FFnGGRSlrJFoyIMu4g41a5HG018rixC3ihhw2GRLWs6UIuUKpUaLjK46anV6g0nI0ms32hFWpmeu2ex3o8lxgVC91Jn0Wq4MADWJLJ2rWLC%2Bhot/sVyrVGnTUNzfPzRfQpLhKrDa2AmAIZUwbEEt3ueBdw4t5qjebxrdJTYRHphpb2/0NyPHzZnxY7yLBEMbUotnaXOuqdDWB0OU/OJnMMrcJLlTAIMqjECnsvlNaDIeRH4XUzzpELbbkapblleqKfgGtbqsi0RASBbbEAiXY9n29CDgQ46juudwTn%2BUEIkh7aSIhW7IXCoYnt2vb9lhOFjvhm6FtukSEWcCGHnyYE6iu6BrrqzHERR7bHLutDgpCXFshakRdmehyXpWN5mCw96Pgoz6vqc75EZEKocRakiAdxImsZRGo0RBlbQd%2BdYNjJvrAaJKHQjR6H0Yw2H4bhQlkgik76SRKHkuRFntgAnGhdGYd5jF4QFLkRW5RlcMcQHUcuioCVGiXTilcKRRJUkHrJfJWaWikXmIkFnKpd4Pm2T4vm%2B/6ROxtkIscpnleZs7ECqGhdjZ7XVoGDnweFA0qlwMUYQO8W%2BUxSVBUa/XFkN02bYupaeXFQ7LflLEzU0lZwmRZkxF2/GCRuG3ISqcIlfuTkWtFNHVcp163upTXoC1OmSHp62RA27XRL1zkhSqx7gRWY1fhNcFldDrkqrxtELQxR3%2BQRXXJTNKrbY98kebFi2HSOK0FTN0iVk9QFcMNNG3XleMnZtnV7tJTNzZ9TDnt9qINX9mnaW1%2BnFQTzNQ7Tm1ZTqo36eNsH1lNV0w5VOr7ZTPnU8dgVGZzj0ZZr6PuXtFM4wbHMPaSKrg6ikgaEzu18Tld3CYTm0ujzqMWlwcOnoLSm1Spv0ac1Wmtbp7VcGd8dwnLJsOx98N1VWSNq45JOki781eVTRw03ya3y49kV58Qkj81b2NLbb90%2B8hLtGZIb1OpjbOnIbLf52d/ud%2BiZNVaHNXfD9alRwDMdAyDgeGTLJnV5I7tlgjKvZ6qKPD/3NfB1jRf6yXffl6nNciubKWSJjus26fdv75IS9TpEZt9ZE6U3Z77PNyFt8Xq8yulwbWawvrhyno1cWsdgbx06vHHqTNLY6hJA8NwAB3Amqsd7qwDnyTAqhCBoAYADR4L4wF4GQCwOIaxMAAEcZYZmdLmTkRx%2BYIkIcQgQZDUAUORNyMoFpsC0CUM9LETAeSuizFfWkrIRFiMlLJX4BAZZhTpBSb0Gi6RYGQAYX4Edp7/UBpLemUZMTwlmqKHRmA9E1DeKYVAeABKixlEwBQVw2Dvjmo8PEKwLEdlkRwGYtBOCRF4F4DgWhSCoE4D4HwAA1AAsmsAAkgAJTWFseYiw0SzV4AQTQwSZgFhAB3GU5Jjjki4IE6IlTqk7lCRwSQESikxM4LwBQIAkSFKicE0gcBYBIDQDQug4RyCUBGXEMZEQ8ALAMEYO4M4%2BB0D7MQLpEAQhtJCP4GozJuC8B2cwJkAB5EI2hbG9J4KQEZWETkMGBG0rAIQ3DACcLVLpBzSBYBYIYYA4g%2BnfLmZcvAphMCfOiYQ2xbg%2BycGuf4DCbTJKcj2S4LAbS7h4BYHC3gYLiAhESJgLUA4/mSSMEUmYVADDAAUAkvAmAMEnLiIwHFMhBAiDEOwKQbL5BKDUG03QTQFnGDUvoPAIQumQBmKgW4KRPkAFoTmdnlb8hYCATwAC8GB4vCTEvFxBnHgvgDMKwIL7AQEcEMRopBfD%2BC6IUHoTQsjJAEFazIiQXUMHGN0CIIx%2Bw2FaAMOorgGh6FNQGgQbRajeodb6ywQa3UjCDTGyYGJZg5K5SEsJrTAWxI4BeYVawIBLMLJiCAuBCAkDyRiApFKSlRGDLU%2BpNSnp1PTE0lppBsXMyRJE6JebOndNIL0rQUws0cDhDm/tHTh11tIHipI9hJBAA)):

```zig
export fn sum(ptr: [*]u64, len: usize) u64 {
    if ((len & 31) != 0 or len == 0) unreachable;
    var a: u64 = 0;

    for (ptr[0..len]) |e|
        a += e;

    return a;
}
```

Gets auto-vectorized like so (x86-64 znver5):

```asm
sum:
        push    rbp
        mov     rbp, rsp
 vpxor   xmm0, xmm0, xmm0
        vpxor   xmm1, xmm1, xmm1
        vpxor xmm2, xmm2, xmm2
        vpxor   xmm3, xmm3, xmm3
        xor     eax, eax
.LBB0_1:
        vpaddq  zmm0, zmm0, zmmword ptr [rdi + 8*rax]
 vpaddq  zmm1, zmm1, zmmword ptr [rdi + 8*rax + 64]
        vpaddq  zmm2, zmm2, zmmword ptr [rdi + 8*rax + 128]
        vpaddq  zmm3, zmm3, zmmword ptr [rdi + 8*rax + 192]
        add     rax, 32
        cmp     rsi, rax
 jne     .LBB0_1
        vpaddq  zmm0, zmm1, zmm0
        vpaddq zmm2, zmm3, zmm2
        vpaddq  zmm0, zmm2, zmm0
        vextracti64x4 ymm1, zmm0, 1
        vpaddq  zmm0, zmm0, zmm1
        vextracti128 xmm1, ymm0, 1
        vpaddq  xmm0, xmm0, xmm1
        vpshufd xmm1, xmm0, 238
        vpaddq  xmm0, xmm0, xmm1
        vmovq   rax, xmm0
        pop rbp
        vzeroupper
        ret
```

However, change the `+=` to `+|=` (saturating addition) and you get no vectorization:

```asm
sum:
 push    rbp
        mov     rbp, rsp
        xor     ecx, ecx
 xor     eax, eax
        jmp     .LBB0_1
.LBB0_17:
        add     rcx, 8
        cmp     rsi, rcx
        je      .LBB0_18
.LBB0_1:
        mov r8, rax
        add     r8, qword ptr [rdi + 8*rcx]
        mov     rax, -1
        mov     rdx, -1
        jae     .LBB0_2
        add     rdx, qword ptr [rdi + 8*rcx + 8]
        mov     r8, -1
        jae .LBB0_4
.LBB0_5:
        add     r8, qword ptr [rdi + 8*rcx + 16]
 mov     rdx, -1
        jae     .LBB0_6
.LBB0_7:
        add     rdx, qword ptr [rdi + 8*rcx + 24]
        mov     r8, -1
        jae .LBB0_8
.LBB0_9:
        add     r8, qword ptr [rdi + 8*rcx + 32]
 mov     rdx, -1
        jae     .LBB0_10
.LBB0_11:
        add     rdx, qword ptr [rdi + 8*rcx + 40]
        mov     r8, -1
        jae .LBB0_12
.LBB0_13:
        add     r8, qword ptr [rdi + 8*rcx + 48]
 mov     rdx, -1
        jae     .LBB0_14
.LBB0_15:
        add     rdx, qword ptr [rdi + 8*rcx + 56]
        jb      .LBB0_17
        jmp .LBB0_16
.LBB0_2:
        mov     rdx, r8
        add     rdx, qword ptr [rdi + 8*rcx + 8]
        mov     r8, -1
        jb .LBB0_5
.LBB0_4:
        mov     r8, rdx
        add     r8, qword ptr [rdi + 8*rcx + 16]
        mov     rdx, -1
        jb .LBB0_7
.LBB0_6:
        mov     rdx, r8
        add     rdx, qword ptr [rdi + 8*rcx + 24]
        mov     r8, -1
        jb .LBB0_9
.LBB0_8:
        mov     r8, rdx
        add     r8, qword ptr [rdi + 8*rcx + 32]
        mov     rdx, -1
        jb .LBB0_11
.LBB0_10:
        mov     rdx, r8
        add     rdx, qword ptr [rdi + 8*rcx + 40]
        mov     r8, -1
        jb .LBB0_13
.LBB0_12:
        mov     r8, rdx
        add     r8, qword ptr [rdi + 8*rcx + 48]
        mov     rdx, -1
        jb .LBB0_15
.LBB0_14:
        mov     rdx, r8
        add     rdx, qword ptr [rdi + 8*rcx + 56]
        jb      .LBB0_17
.LBB0_16:
        mov     rax, rdx
        jmp     .LBB0_17
.LBB0_18:
        pop     rbp
 ret
```

With more manual vectorization, I can get this emit:

```asm
sum2:
        push    rbp
        mov     rbp, rsp
 vpxor   xmm1, xmm1, xmm1
        vpxor   xmm3, xmm3, xmm3
        vpxor xmm2, xmm2, xmm2
        vpxor   xmm0, xmm0, xmm0
        xor     eax, eax
.LBB1_1:
        vmovdqu64       zmm6, zmmword ptr [rdi + 8*rax + 128]
        vmovdqu64       zmm5, zmmword ptr [rdi + 8*rax + 64]
 vmovdqu64       zmm4, zmmword ptr [rdi + 8*rax]
        vmovdqu64 zmm7, zmmword ptr [rdi + 8*rax + 192]
        add     rax, 32
 vmovdqa64       zmm8, zmm6
        vpternlogq      zmm8, zmm6, zmm6, 15
 vpminuq zmm2, zmm2, zmm8
        vmovdqa64       zmm8, zmm5
 vpternlogq      zmm8, zmm5, zmm5, 15
        vpminuq zmm3, zmm3, zmm8
 vpaddq  zmm2, zmm2, zmm6
        vmovdqa64       zmm6, zmm4
 vpternlogq      zmm6, zmm4, zmm4, 15
        vpaddq  zmm3, zmm3, zmm5
 vmovdqa64       zmm5, zmm7
        vpternlogq      zmm5, zmm7, zmm7, 15
 vpminuq zmm1, zmm1, zmm6
        vpminuq zmm0, zmm0, zmm5
 vpaddq  zmm1, zmm1, zmm4
        vpaddq  zmm0, zmm0, zmm7
        cmp rsi, rax
        jne     .LBB1_1
        vmovdqa64       zmm4, zmm3
 vpternlogq      zmm4, zmm3, zmm3, 15
        vpminuq zmm1, zmm1, zmm4
 vmovdqa64       zmm4, zmm2
        vpternlogq      zmm4, zmm2, zmm2, 15
 vpaddq  zmm1, zmm1, zmm3
        vpminuq zmm1, zmm1, zmm4
 vpaddq  zmm1, zmm1, zmm2
        vmovdqa64       zmm2, zmm0
 vpternlogq      zmm2, zmm0, zmm0, 15
        vpminuq zmm1, zmm1, zmm2
 vpaddq  zmm0, zmm1, zmm0
        vextracti64x4   ymm1, zmm0, 1
 vmovdqa ymm2, ymm1
        vpternlogq      ymm2, ymm1, ymm1, 15
 vpminuq ymm0, ymm0, ymm2
        vpaddq  ymm0, ymm0, ymm1
 vextracti128    xmm1, ymm0, 1
        vmovdqa xmm2, xmm1
        vpternlogq xmm2, xmm1, xmm1, 15
        vpminuq xmm0, xmm0, xmm2
        vpaddq xmm0, xmm0, xmm1
        vpshufd xmm1, xmm0, 238
        vmovdqa xmm2, xmm1
        vpternlogq      xmm2, xmm1, xmm1, 15
        vpminuq xmm0, xmm0, xmm2
        vpaddq  xmm0, xmm0, xmm1
        vmovq   rax, xmm0
 pop     rbp
        vzeroupper
        ret
```
</pre>
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GwbwF0a-VIY9UhbPQ-eHQ0YSM7G8vLWIMcu_QfeK8oFCFKNfQvnyhb4H2fF-Wp-Ox-htVtynYTj9D5RVzfn0ulofErFt2g95fb7GXTO2bdy9edjFw68FR2ym-Bx3N61h6tdJvBzSeHkT3yvYgkSWQ_PzO8U8P1pgdO8PY-cPWZ3cYikbsqa-FUO_jpaXZlwm8bCsm-XPKubf5X9brP6kSn0sCeFTSQjvwfqwUPx8JX-O79dIfv5Eva8hLznypJr-IkXCd_qfEuWnfvqzGnXzq6PfpNhHu3fZ6dPcDuf3Of3C05PTf6GPZNGvstx_m9nYIyRPb30F5fnzY0D0Q5tP9ogXelaf0P-3NDyVOPLZ-O-7Sr6Y_mzlf9NvjPgHjr_Gxfq_chzH_thxFHmNSfS_c51A_oHrKPZqH_-vnCfoP3f-NeLQz0LuN51fke-dz4PlW0PUh6Lz_Pg17LBfC8Ib8x39_ycVg-XP_PuJi_gE11Oxiv5ZsXqfpY9dfgyMegFG_u8I-5Mc_gls_QKM_p8xhmP_gDH0za6G_O84-5Pkf4GGv0L7LP7_e9aIz-L_S9ZeMwD9LAX-BdZ-o2q8VIrHIJ42-PcEfTjVvNHyITZvx8Xl6yHr4bFwnw3psmq6eFn59eiXHw5yGLOUlqFf3495Q5r1y7jKhi_Od9i_chv9-2vm394g__Q2-tUF-NPbKPrLbbRqztFpJInn79eqIv_xLfBXXas_vZw-0EH89u34FxzXqqL-1Xvok2r_LTz62QD5bpmGuKvLJjk9mPZmvKf18txWWT2eHt3E6V_cemj7Wc2nRldvxyejL0hfbH-8udMfGg4fsZFfY_vpKPEJtlf5m_EDtk-7CqtPFuOno9TXi_E67c34y2J87LCQj3n7eHdf_U2jhvi9FgD14VL3vufx_O9t6wP9z8eL-QdyiBcSH68I8YFk_KtoeejVF0axr1eE-BBc2NsV-ZRK_E-wfa4G-5q3d12eB9ixDyuH_Alv2AdsX_ap3rWWlo-bS88O3ITYc6cI_YL7d9PejO-z4We76c34qDX2YNoTprctrDc75sMu1jP-NzvgJ_jfzXgzPqT-wY75wIN_p3X22x4sn8n4t934h127D-evn5N_o2X3LfqBR2t87X-Lf6AUgWEoiuPrb-mPkCJDLFihYbAOYz_E4jBG11joryMMCeJV9C37gSHYCsFRCkXxFb7-jsYBgfoRgdB-jER4vCCQuPKz8vv9lzhNl3zL-n6Mf6A4SiLot9IP4rK__2AWw-p4Wt6lC-y2m3_rftxe-isYk35BIGXWD_2rmiEbyvgHePdfGssHzcNvY1f-eP-joCQb0jH4HjbV8y-Enoe_2q7J43BYYPwdRr_A-Gec5x_Y_wsAAP__eGTJjg">