<table border="1" cellspacing="0" cellpadding="8">
<tr>
<th>Issue</th>
<td>
<a href=https://github.com/llvm/llvm-project/issues/131478>131478</a>
</td>
</tr>
<tr>
<th>Summary</th>
<td>
[MachineCopyProp, SystemZ] "Using an undefined physical register"
</td>
</tr>
<tr>
<th>Labels</th>
<td>
backend:SystemZ,
llvm:codegen
</td>
</tr>
<tr>
<th>Assignees</th>
<td>
</td>
</tr>
<tr>
<th>Reporter</th>
<td>
JonPsson1
</td>
</tr>
</table>
<pre>
MachineVerifier reported *** Bad machine code: Using an undefined physical register ***.
git bisect shows
```
commit 2def1c4 (HEAD, refs/bisect/bad):
[RISCV][MCP] Remove redundant move from tail duplication (#89865)
Tail duplication will generate the redundant move before return. It is
because the MachineCopyPropogation can't recognize COPY after post-RA
pseudoExpand.
This patch make MachineCopyPropogation recognize `%0 = ADDI %1, 0` as
COPY
diff --git a/llvm/lib/CodeGen/MachineCopyPropagation.cpp b/llvm/lib/CodeGen/MachineCopyPropagation.cpp
index b34e0939d1c7..fab36f4858e0 100644
--- a/llvm/lib/CodeGen/MachineCopyPropagation.cpp
+++ b/llvm/lib/CodeGen/MachineCopyPropagation.cpp
@@ -1053,7 +1053,7 @@ void MachineCopyPropagation::BackwardCopyPropagateBlock(
// Ignore non-trivial COPYs.
std::optional<DestSourcePair> CopyOperands =
isCopyInstr(MI, *TII, UseCopyInstr);
- if (CopyOperands && MI.getNumOperands() == 2) {
+ if (CopyOperands) {
Register DefReg = CopyOperands->Destination->getReg();
Register SrcReg = CopyOperands->Source->getReg();
```
This changes the result of MachineCP on this test case like:
```
old <> failing
*** IR Dump After Machine Copy Propagation Pass (machine-cp) ***
renamable $r14d = LLILL 0 | renamable $r12d = LLILL 0
renamable $r12d = COPY killed renamable $r14d, implicit-def $r12q <
renamable $r14l = LMux %fixed-stack.11, 4, $noreg :: (load (s32) fro renamable $r14l = LMux %fixed-stack.11, 4, $noreg :: (load (s32) fro
renamable $r14l = LLHRMux killed renamable $r14l renamable $r14l = LLHRMux killed renamable $r14l
renamable $r3l = LMux killed renamable $r3d, 12, $noreg :: (load (s3 renamable $r3l = LMux killed renamable $r3d, 12, $noreg :: (load (s3
renamable $r11d = LGFR killed renamable $r3l, implicit-def $r10q renamable $r11d = LGFR killed renamable $r3l, implicit-def $r10q
ST128 killed renamable $r10q, %stack.5, 0, $noreg :: (store (s128) i ST128 killed renamable $r10q, %stack.5, 0, $noreg :: (store (s128) i
renamable $r10q = COPY killed renamable $r12q renamable $r10q = COPY killed renamable $r12q
*** IR Dump After Post-RA pseudo instruction expansion pass
renamable $r14d = LLILL 0 | renamable $r12d = LLILL 0
$r12d = LGR killed $r14d, implicit-def $r12q <
renamable $r14l = L $r15d, 380, $noreg :: (load (s32) from %fixed-st renamable $r14l = L $r15d, 380, $noreg :: (load (s32) from %fixed-st
$r14l = LLHR killed $r14l $r14l = LLHR killed $r14l
renamable $r3l = L killed renamable $r3d, 12, $noreg :: (load (s32) renamable $r3l = L killed renamable $r3d, 12, $noreg :: (load (s32)
renamable $r11d = LGFR killed renamable $r3l, implicit-def $r10q renamable $r11d = LGFR killed renamable $r3l, implicit-def $r10q
STG $r10d, $r15d, 184, $noreg, implicit $r10q :: (store (s128) into STG $r10d, $r15d, 184, $noreg, implicit $r10q :: (store (s128) into
STG killed $r11d, $r15d, 192, $noreg, implicit killed $r10q :: (stor STG killed $r11d, $r15d, 192, $noreg, implicit killed $r10q :: (stor
$r10d = LGR killed $r12d, implicit $r12q $r10d = LGR killed $r12d, implicit $r12q
$r11d = LGR killed $r13d, implicit killed $r12q $r11d = LGR killed $r13d, implicit killed $r12q
*** Bad machine code: Using an undefined physical register ***
- function: t
- basic block: %bb.0 (0xade6dc0)
- instruction: $r11d = LGR killed $r13d, implicit killed $r12q
- operand 2: implicit killed $r12q
LLVM ERROR: Found 1 machine code errors.
```
With the LGR (left), there is an implicit-def of $r12q.
In the failing version (right), I see MachineCP propagating a COPY, but while doing so dropping the implicit-def of $r12q:
```
*** IR Dump After Greedy Register Allocator (greedy) ***:
528B %53:gr64bit = LLILL 0
544B undef %58.subreg_h64:gr128bit = COPY %53:gr64bit
636B %57:gr128bit = COPY %58:gr128bit
*** IR Dump After SystemZ Post Rewrite pass (systemz-post-rewrite) ***:
renamable $r14d = LLILL 0
renamable $r12d = COPY killed renamable $r14d, implicit-def $r12q
renamable $r10q = COPY killed renamable $r12q
*** IR Dump After Machine Copy Propagation Pass (machine-cp) ***
renamable $r12d = LLILL 0
renamable $r10q = COPY killed renamable $r12q
*** IR Dump After Post-RA pseudo instruction expansion pass (postrapseudos) ***:
renamable $r12d = LLILL 0
$r10d = LGR killed $r12d, implicit $r12q
$r11d = LGR killed $r13d, implicit killed $r12q
```
*** Bad machine code: $r12q is undefined in last LGR as $r13d never had a definition.
The MIR looks legal up until MachineCP, so maybe something is missing there?
[tc_gr128CopyExp.tar.gz](https://github.com/user-attachments/files/19266599/tc_gr128CopyExp.tar.gz)
llc -mcpu=z15 -O3 -disable-cgp -use-mbpi=false -greedy-reverse-local-assignment -aggressive-machine-cse -misched=ilpmin -verify-machineinstrs ./tc_gr128CopyExp.ll
@BeMg @arsenm @efriedma-quic @asb @jsji @vladimirradosavljevic @uweigand
</pre>
<img width="1" height="1" alt="" src="http://email.email.llvm.org/o/eJy8WV9zozgS_zTKSxcuEGDjhzz4Tzzrq-Qm5Zndq7uXLYEarIlAjCScZD79lQROnMRO9nLJUq4Co9avW92tn9SCGSOqBvGcpHOSLs9YZ7dKn_9DNdfGqCY6yxW_P79ixVY0-AdqUQrUoLFV2iIHQmf9D-aMQ92LQaE4kngGvxvRVMAa6BqOpWiQQ7u9N6JgEjRWwljUjxAjEs5IOKuEhVwYLCyYrbo1_VsyDodfOCtUXQsLlGMZFQkQmv12MVsSugCNpSF01Xd3D4wTOiXxrAcBks4362-LP0i6JOn8anFN0iVssFY7BI28azhrLPi_pVY1WCYk8K6VomBWqAacMkLjbJqNU4cczgAA3O37c9FbISVU2KBmFsFuX2jIsVTavbWdbkawtiDcYCHHgnWm7zI4fqHa-2utWlX12AVrCJ1Y0FioqhG_EBZfr_8NrHQObZWxwcaPtzXYcXVx17KGjw6MBYDvW2GgZbbYQs1uTmp61OB8T9MQSLyE2XK5BkLTyDndRQWYGXCdIb23uShLCAIXT0boSspd7W4iJ3S1UBy_YEPo6ple1usdFW0L-Xt6kXAmGo53kMcJhtN4yqNiMhqVLI_HZZKlGYYQheE4SUg4C4Lgfba5EdJ5_3u3nSQJSRJCEIVpTOhiAoTOH5_7xp0S_HlsBhSX1vFszoqbW6b5YSPOpSpuXKr2MQFCV4SuYF01LuMa1QRWi51g0ofL7FMDjOU9qmqdBiZJvFiisd9Upwu8ZkKT-AKcqq8tatZw49LB9RbGvV03xmpCs6u1SwxCZ9_X_ul3gwfNUxLPnfOdRlG6KfUUkY4JHcPVelSh_WdX7xv81Jt6hfESqH-ezPtIHId6FIH-2uxJZ4nlBiufy4cdAhJfuPGKxnvY_a3QbrDqdfd2P8f6potTWL3fjsM8IzUSzvyULLasqdAMhGE6aUGVDxlwDaoB6-QsGgsFMwhS3OADxR1CKsmBxAsXspIJKZpqkHkg7fUGll3dwswTx6DEjwIOEg2umXFhyQZ-D4rWe3YPM5AraGxYzXKJQGiio4R7n1xeri8vIQQyWQyeeyZHn8gdQxokPMfdCCmRv9Tl0kzUjn6FDTiWQ8-f3gPHrJO91qvuzjFZKe6QB8ay4mYUeVpL-hRO3JRx0XXTwjlBKubWvczEPgVLrT4R2ll-Av3yt41TcMIf8p3djrgqPhjO0W6xd35E3xwVHFyfpeNYrKMhw76sNifQ5fH0CX_Cs-vjkL2h375HNDsRjPBnP9i0T520X2uPj99YR-zuIepZUhwa_Xlajnk7_PnWbKUv3Hrkegfq6_R23e-Lhk0RCLcYdYUnOHQ7JOOeWmbMx_PZk_dfHlLlLep65XqD1fp_qYeOs1PxfMk39SFhvRKND9Xz6KIDknrqI_lW-yu89X8Sijf585A_mq8-nKC-DP_5MJ59uKPsyTJ2iHIwY09TR2PVJ6M_DOAwVaIXmqb0pKbDji8UfiL044wIj5MG5S894vY6_3OXR03R8W4xP2n2X6DxdyPvC_YPPF9weAGUXVMM1ZMz0PZvc2ZEAbkvm3wY0jwfhb7cD-8YxzEvwqHeDw5Xjl74_WOEAFRfLwDtLXpF9vLyjyu42Gy-bpzoSnUNh-iJUwC1VtqMjpYX_xJ268sKZ6QjIiytGxNduLcaQRjnyydUoB4WowFz3XiIoZ6AHWq_bBKaaVFt93hrMIgHRUu7LyZcuPojArqAvLNwuxUSgSvXYhRwrdrWPTslJyw5WuvAqVX_i0bk94_V2kxKVTA3fQnNKt_4tJjZo6c0m--TOE1jEs8qPU5yN3WerO5pkgxyPgu9dDYyXa6x-nM7TnzHiGb7nn4H8wyShLNxPD5QNznZKztoeTFJng79272xWP_Hb3xgg7daWPQbHE8zvvFX4E-LdN943BFvbIQ-umB775byb61t365Z_8b9qjPfhVGzXtT8xTie2qj-jQuIT99nTPUq5e8XHmEOSF80IJmxXjUze7XQ4A41bBkHBl5U-MO3_WELwtV6A1KpGwMSKyaha6FrrJCPzOVMNwpqdp8jGFWj3Tp2EgZqYcxAVBpJvBpimc5t8aefny7TLu7akWV6VP0i6ZLQbGtta1xA_HlcJey2y0eFqglddQZ1wKxlxbbGxhpCV6WQ6O7RlI7H6XRK6OoEuF-ZpCwgqIu2I_HyV5RC8DUGCLgwLuJBUbUQdAaDOm8FiZclkwYh6Bkw0M5VBgPHjTLoPwo4MyBgVaXRGLHD4GGKuI61MMUWOYmXQra1aCDYoRbl_V7Kp6uB0RGjpRyclYRzvKqAJCHTBpvaPWGpBfKaBT87Ufgmk7vbD_NDuPtOMi5qoTXjyrCd_IG7Xq67RVG5hbQHP-PnMZ_GU3aG59EkoeFkHGbx2fYcExbl2TSi03RaFkk2zqZsOk5YEdOsjCN-Js5pSNMwjlJKw4jGo5JPpkk6ySc8m2ZTyp2VNRNyJOWuHildnQljOjyP4iiZZGeS5SiN_6BCac6KG2w4iWcDGxPq9oSEUn9iHM9cYlfYuNfp8kyfu9dB3lWGJKEUxppHLVZY6T_UPDsPdkm6R0-XQCj9KxsjQulZp-X5Kzm5P9R2JrVa_eg_qvjB-rzsx7s7p_8NAAD__z7oyIU">