<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/130217>130217</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            [RISCV] Add assembler support for the Q extension
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            backend:RISC-V
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          topperc
      </td>
    </tr>
</table>

<pre>
    I don't know of any hardware that implement this, but the opcodes are standardized and it is implemented in the binutils assembler. I think the cost of supporting in LLVM is relatively low and it could be a good first task for someone.

Thoughts @asb @jrtc27 @preames @lenary?
</pre>
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