<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/130245>130245</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            AMDGPU misses general case to match s_bitset instructions
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            backend:AMDGPU,
            missed-optimization
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          arsenm
      </td>
    </tr>
</table>

<pre>
    We currently do not try very hard to make use of s_bitset0_b32/s_bitset0_b64 or s_bitset1_b32/s_bitset1_b64

```
; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 -o - %s

; s_lshl_b32 s1, 1, s1
; s_or_b32 s0, s0, s1
; This can emit s_bitset1_b32
define amdgpu_ps i32 @s_bitset1_b32(i32 inreg %src0, i32 inreg %bit.index) {
  %set.bit.at.index = shl i32 1, %bit.index
  %or = or i32 %src0, %set.bit.at.index
  ret i32 %or
}

; s_lshl_b32 s1, 1, s1
; s_andn2_b32 s0, s0, s1
; This can emit s_bitset0_b32
define amdgpu_ps i32 @s_bitset0_b32(i32 inreg %src0, i32 inreg %bit.index) {
 %set.bit.at.index = shl i32 1, %bit.index
  %other.bits = xor i32 %set.bit.at.index, -1
  %and = and i32 %src0, %other.bits
  ret i32 %and
}

```

We only recognize and / or with a constant in SIShrinkInstructions. We should be able to recognize cases with a bit set to a variable index 
</pre>
<img width="1" height="1" alt="" src="http://email.email.llvm.org/o/eJykVE2P6yYU_TV4c-UIgz2JF154Jkr1Fq2qvj7NcoTNHZsOhoiLp5P36ytI5ivtoq-VSFC455zLOQQUkZkcYseaW9bsC7XG2YdOBUK3FIPXp-4eYVxDQBftCbQH5yPEcIJnDCeYVdAQPSzqCWElBP8I9DCYSBj5wyAFE4cPv29q8OENUF0BqgRgvE_jhl8G75m8hd--_cJkD9aOUC4xmKNFJvdq0dPoSrXo9DkqC-UyHlcm99PjS8s5lB5KYKKhi6q8BXqwNNvUGahi4g7yF1VvZR_ORZ7X-afq77MhGJUDXEy88sF7jY_GIaRdHdeHI4GRAljNr_zu0rJxAae8tTDmHp8WBxM3xml8YaIFtr1lvIcMxrhJNXUpA5N7oNlmdjbyiXxh-ZBxPpw39N7zHxQzJ2B8hfqQrG_3PxCgctqJH82Q_8sM-f_K8L9HGGcMiUcZ__Ihy-sAxR2U1StPOZ0Jaf57-O-q17Erpz_l_vE68P4ewTt7goCjn5z5jlmfiUM64z9NnEHB6B1F5SIYB1-_fJ2DcU9fHMWwjtF4Rxu4R6DZr1bDgKAGi-kiv0uOipBe1YZ0VBgTQsGzCibjzwEWupO6la0qsKu2dSVFLcS2mLt6HOpatYPaoUbEXVPpqn3EkUsltnhTFaYTXDRc8i1vKi62m51oVIWtbHm149gOrOa4KGM31j4vGx-mwhCt2FWSi7oprBrQUn67hBjU-IROM9n3P-9_-vUbE4KJOybEYohQl_4YzWK-q-Q-1Zp9EbqkWw7rRKzm1lCk907RRIvdWQuyBsGEDoOyOZvzsxfH-e0_DOZDvsUabDfHeCQmeyYOTBwmE-d12Ix-YeKQ-lym8hj8HzhGJg7ZHjFxuDh87sRfAQAA__-DgLv-">