<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/130191>130191</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            [HLSL] Typed buffer with signed int vector is translated as unsigned
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            bug,
            HLSL
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
            hekota
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          hekota
      </td>
    </tr>
</table>

<pre>
    The target type generated for `RWBuffer<int4>` does not have its `isSigned` field set to `1` and the resource is treated as unsigned. This probably applies for all typed buffers with integer vector element types.

```
RWBuffer<int4> Buf : register(u0);

[numthreads(4,1,1)]
void main() {
    Buf[0].x = 42;
}
```
Clang:
```
%"class.hlsl::RWBuffer" = type { target("dx.TypedBuffer", <4 x i32>, 1, 0, 0) }
@Buf = internal global %"class.hlsl::RWBuffer" poison, align 4

; Resource Bindings:
;
; Name Type  Format         Dim      ID      HLSL Bind     Count
; ------------------------------ ---------- ------- ----------- ------- -------------- ---------
; UAV     u32         buf      U0             u0 1
```
DXC:
```
; Resource Bindings:
;
; Name Type  Format         Dim      ID      HLSL Bind  Count
; ------------------------------ ---------- ------- ----------- ------- -------------- ------
; Buf                                   UAV     i32 buf      U0             u0     1
```
</pre>
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