<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/129929>129929</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            Segfault when lower COPY intrinsic RISCV
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            new issue
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          bababuck
      </td>
    </tr>
</table>

<pre>
    Built info:
Hash: `edc02351dd`

Command:
```
$LLVM_DIR/bin/llc o3.ll -march=riscv64 -mattr=+v -O3  -o output.s
```

Trace:
```
PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace.
Stack dump:
0.      Program arguments: /work/rbuchner/llvm/build//bin/llc o3.ll -march=riscv64 -mattr=+v -O3 -o output.s
1.      Running pass 'Function Pass Manager' on module 'o3.ll'.
2. Running pass 'Post-RA pseudo instruction expansion pass' on function '@strlen'
 #0 0x0000000001ce5388 llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/work/rbuchner/llvm/build//bin/llc+0x1ce5388)
 #1 0x0000000001ce2bac SignalHandler(int) Signals.cpp:0:0
 #2 0x00007fde7f664d10 __restore_rt (/lib64/libpthread.so.0+0x12d10)
 #3 0x0000000000861bc7 llvm::RISCVInstrInfo::copyPhysRegVector(llvm::MachineBasicBlock&, llvm::MachineInstrBundleIterator<llvm::MachineInstr, f
alse>, llvm::DebugLoc const&, llvm::MCRegister, llvm::MCRegister, bool, llvm::TargetRegisterClass const*) const (/work/rbuchner/llvm/build//bin
/llc+0x861bc7)
 #4 0x0000000000862e57 llvm::RISCVInstrInfo::copyPhysReg(llvm::MachineBasicBlock&, llvm::MachineInstrBundleIterator<llvm::MachineInstr, false>,
 llvm::DebugLoc const&, llvm::MCRegister, llvm::MCRegister, bool, bool, bool) const (/work/rbuchner/llvm/build//bin/llc+0x862e57)
 #5 0x00000000010afbf4 llvm::TargetInstrInfo::lowerCopy(llvm::MachineInstr*, llvm::TargetRegisterInfo const*) const (/work/rbuchner/llvm/build/
/bin/llc+0x10afbf4)
 #6 0x0000000000d21618 (anonymous namespace)::ExpandPostRA::runOnMachineFunction(llvm::MachineFunction&) ExpandPostRAPseudos.cpp:0:0
 #7 0x0000000000e4ea73 llvm::MachineFunctionPass::runOnFunction(llvm::Function&) (.part.69) MachineFunctionPass.cpp:0:0
 #8 0x000000000136d581 llvm::FPPassManager::runOnFunction(llvm::Function&) (/work/rbuchner/llvm/build//bin/llc+0x136d581)
 #9 0x000000000136d701 llvm::FPPassManager::runOnModule(llvm::Module&) (/work/rbuchner/llvm/build//bin/llc+0x136d701)
#10 0x000000000136e144 llvm::legacy::PassManagerImpl::run(llvm::Module&) (/work/rbuchner/llvm/build//bin/llc+0x136e144)
#11 0x000000000082ceae compileModule(char**, llvm::LLVMContext&) llc.cpp:0:0
#12 0x0000000000774c06 main (/work/rbuchner/llvm/build//bin/llc+0x774c06)
#13 0x00007fde7e0bf7e5 __libc_start_main (/lib64/libc.so.6+0x3a7e5)
#14 0x0000000000824ade _start (/work/rbuchner/llvm/build//bin/llc+0x824ade)
```

Input file:
```
; ModuleID = '../o3.ll'
source_filename = "loop.c"
target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
target triple = "riscv64-unknown-unknown"

; Function Attrs: nofree norecurse nosync nounwind memory(argmem: read) vscale_range(2,1024)
define dso_local noundef signext i64 @strlen(ptr noundef %0) local_unnamed_addr #0 {
  br label %2

2:                                                ; preds = %1
  %3 = phi ptr [ %0, %1 ]
  %4 = call { <4 x i64>, i64 } @llvm.riscv.vleff.v4i64.i64(<4 x i64> undef, ptr %3, i64 4)
  %5 = extractvalue { <4 x i64>, i64 } %4, 0
  %6 = extractvalue { <4 x i64>, i64 } %4, 1
  %7 = icmp eq <4 x i64> %5, splat (i64 1)
  store <4 x i1> %7, ptr %3, align 1, !tbaa !8
  ret i64 %6
}

; Function Attrs: nocallback nofree nosync nounwind willreturn
declare { <4 x i64>, i64 } @llvm.riscv.vleff.v4i64.i64(<4 x i64>, ptr nocapture, i64) #3

attributes #0 = { nofree norecurse nosync nounwind memory(argmem: read) vscale_range(2,1024) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv64" "target-features"="+64bit,+a,+d,+f,+m,+relax,+v,+zaamo,+zalrsc,+zicsr,+zifencei,+zmmul,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b,-b,-c,-e,-experimental-sdext,-experimental-sdtrig,-experimental-smctr,-experimental-ssctr,-experimental-svukte,-experimental-xqcia,-experimental-xqciac,-experimental-xqcicli,-experimental-xqcicm,-experimental-xqcics,-experimental-xqcicsr,-experimental-xqciint,-experimental-xqcilsm,-experimental-xqcisls,-experimental-zalasr,-experimental-zicfilp,-experimental-zicfiss,-experimental-zvbc32e,-experimental-zvkgs,-h,-sha,-shcounterenw,-shgatpa,-shtvala,-shvsatpa,-shvstvala,-shvstvecd,-smaia,-smcdeleg,-smcsrind,-smdbltrp,-smepmp,-smmpm,-smnpm,-smrnmi,-smstateen,-ssaia,-ssccfg,-ssccptr,-sscofpmf,-sscounterenw,-sscsrind,-ssdbltrp,-ssnpm,-sspm,-ssqosid,-ssstateen,-ssstrict,-sstc,-sstvala,-sstvecd,-ssu64xl,-supm,-svade,-svadu,-svbare,-svinval,-svnapot,-svpbmt,-svvptc,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xsfcease,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xsifivecdiscarddlone,-xsifivecflushdlone,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-xwchc,-za128rs,-za64rs,-zabha,-zacas,-zama16b,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmop,-zcmp,-zcmt,-zdinx,-zfa,-zfbfmin,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zihintntl,-zihintpause,-zihpm,-zimop,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-ztso,-zvbb,-zvbc,-zvfbfmin,-zvfbfwma,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl4096b,-zvl512b,-zvl65536b,-zvl8192b" }

!llvm.module.flags = !{!0, !1, !2, !4}
!llvm.ident = !{!5}

!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 1, !"target-abi", !"lp64d"}
!2 = !{i32 6, !"riscv-isa", !3}
!3 = !{!"rv64i2p1_m2p0_a2p1_f2p2_d2p2_v1p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"}
!4 = !{i32 8, !"SmallDataLimit", i32 0}
!5 = !{!"clang version 20.0.0git (https://github.com/llvm/llvm-project.git edc02351dd11cc4a39b7c541b26b71c6f36c8e55)"}
!6 = distinct !{!6, !7}
!7 = !{!"llvm.loop.mustprogress"}
!8 = !{!9, !9, i64 0}
!9 = !{!"omnipotent char", !10, i64 0}
!10 = !{!"Simple C/C++ TBAA"}
```

More debug info:
Looks like the the instruction being lowered is: `renamable $v8m2 = COPY killed renamable $v8m4, implicit $vtype`

The segfault arise because of the following code, where `TRI->getCommonMinimalPhysRegClass(SrcReg, DstReg);` returns a nullptr because there is no minimal class for `V8M2` and `V8M4`:
```cpp
  const TargetRegisterClass *RegClass =
 TRI->getCommonMinimalPhysRegClass(SrcReg, DstReg);
  if (RISCVRegisterInfo::isRVVRegClass(RegClass)) {
    copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RegClass);
    return;
```
</pre>
<img width="1" height="1" alt="" src="http://email.email.llvm.org/o/eJy8Wl9z46iy_zTKC2WXhGTZfsiDnUzqpO5MbSrZmqr75EIIyVwjUAApTj79rQb0x4nPnjuztXdq1_xomqa7aaARIcbwWjJ2G6320er-hnT2qPRtQQpSdPR0U6jy_XbfcWERl5WK0l0U7_5FzDFKdyjKY1bSGKerpCyjPI5iaL1TTUNk6VmB6v-LdxHOvn__-eNw__gc4YeCywg_CEGRSpdCoEVDND1G6b3mhvZ5BgRrdZTeR3jfo8UfKUILhVRn284uzWfZ8e5PTSj7OurT92-7l2_IdEXDLSKo6GqkWau0RVaho7WtgU74IcIPNbfHrlhS1TjV-qFYtFr9D6M2wg_cmI6ZCD8gIkvEJRVdyZA9MkQ1MUdUEHqyoMkyincvltATKrum9XrFS-T-PWlVa9IgouuuYdIa50388Kb0KcIPuujoUTI9KVF0XJRex9_w26XbkqDEcycllzVqiTEowuuHTlLLlURPQPhBJKlBhTVSEjWq7AQDLjdohNdgHl5-EfKkjF0871BrWFcqxKWxuvNi2bkl0gAC5iC4GgaN8DrKYmO1YBJwDA5JYxSf4-FfQtkq3WyQ80m6i9KdeTcePGkurfO2jwK8mZg0eTsoYzUjTYTzCN8hLm2EtyjCm1_1eYT38TnoEeFt0DL5pCUuCEUvvJZE_IvIUoDUTRjUk82SthATsfvfS8FByroq2brK86xMYnQ4aGas0uygbVBY8CLPfNnao2akXBq1jL1quEziSbF0rli8yZOCrmfue358ufv5CFP0GNZ2uqOqfX86vptnVv9k1Cp94csfhB65ZHtiON0LRU_Bo184nNR9B8Y_WqYJCErvrrOBgCqKd0QYFqXfLuXds6KrvyuKqJLGfh3u7pnV3Fim_4peKCUu2_8kumZ24LkTEL5hhB1Mk8O_GCGww41B4p09TUX2aSowW_3CVPw_TcI0A6D1PzQJl-XvuXruZ_Dk5OfVxVqMSVVU2Zd5_-Rood6YvlPt-zU3B-_s_ip-QNTfCB8XOJ_2GK_5ZFd-ET8lTvJkAwMQqeR7ozqDJGmYad3ut_VKfoMdt4Qt-XkX9sJO_iGDYcN-f83oqS0Hc-aCntzOfm0DW1-oyDJG1unXoBxEwykzU-qqNp_UiPBm2RJtl_kWqlcEXtFqcxEQaV6uNslMq4cn6Decdr-sz-8dIF6LaXK3n3Vcx_8XHX-4U_ly_gLpb-u3joN-cL7Fn_RjSTZfVILVhL6Hk3jS9LFpxajtP6Il6DFpmVxusZgywhBVTcsFG11Fj8Sv5k8LGjLTOyUtO9uglxD0UzjBIPhikPU6o3GOGsLlb9vhZUxmpPM8gMVFtWYrdDgIXtCDsUTbw2y4WTJAIQ3InciUrNlqkvjp7MEZKRnysn5_33VSwhiXifijbDuLKi6uZONRukd-Lh7vUZTeQ963XEb4Ycgro3hnVKcpO4AA2NMCGxZKtUsaYRzFO-u2X1QSSwR5V50dmNgC5pMtYNryzP0s-AgSvInSXYI3C5liT3sB2lym1bwV46AhqV508iTVmxxK3yPYMybOO2u1S-WlqjRjSCrNaKcNIPMuKZKqk29clqhhjdJw3BBdNwxURpDIQdj1hhLBDprIGuIVR_guiXEI85JVXDJUGnUQihLhJJasQu4Wd7aI5xma5dGb1uqRJ8Kr2AU29Dx0EpxbHkhZap9qR-s97Eeo0EiQggnoEMwEZ6Ff_AeuaTUrTfDlKnHSI7xKHaU9cgTqRat9UO3OcaFodT9wZo6TEiFAOxSldxk6IzehLk905q7vwWQI2KWbrmUvWFUt-4zn2RJ4YdZnHZFzB3R3w-NVOogazlsgrtzQ7AyXOdsT0bH_oAJeZVCPBwH5bwoY3bR2AjhtWsReL_s5BYHZtIK4RQxShhMFuRvD2CMJHdafTSaC1xJ6geMTWxAC5caJ0CwEE17lEAPr-78OeJgjuPtOsX8Z8W9cCM1sp6ULYyqI_k_--JU5HUwDRVrbaRYk-QMmTb3ycDHmRWeZCREPgbne_0PrFfYPqRZWk7blsoZ7-RE2DriZY6s7FmEMPAburYtWK-suXIuiqyqmF4Z_sJF9E3j9JrWgbTc21UwyzelC92DunKtiBFxhRtYI7_Os4BYSfLwnvih9Ufmi8YVmgpw97H3xQUijBii0oQFzavQAKyYp46HWNJ0IsGcprmb4POI8K2e4muGRRyR4U4yVFE84zwAv3A-os2Du59wyzRsmLRELU7oD_QvVal5_JTfUXYQ-Uc1Vat-d7Nfxzq-Uk-tUepVMBb9Ob66Tzb8hf9UQ6O6jwxW6MNfFG_FV_gcR5Ir4D04rLtrrdHNFTF_QFH_12Ed_qh33EX7MkfiCqk5appl88_Wa2DY0wWYaYG8mcm8uGmzPaOkqDfFTYhpaMsHqgI3mMjCUhbC69Zi1TUBN23ggB6Blwz0yllgGJ-zdwphBvqG0qgfU-qAxhqqqbaoBX1hlZkqYmRJmGNEM5asyPPBdDG2s5tR6bGkoRzfMnGC6PDsLB7sgtHcJnAedBwXRgcRlTzx7L0mr_BB9WzQB9a0f7kzhaAuo4COwDZG8DVUm3gJqyNALtlGPDG-cjmdTUUYMC7in7YAqqang7bl6rUbSW0MofX19HQivUC9VeVF_VaGdVxxcwQ0luiyFkmxOr0RnjhPVHhkpCzLDxQybCVO3Iw4VJctG9ROhaljDy_NEGIz3lc-NrGkJ1xMBTqCp1pd-Ds49LBtJYDTVel3e6NFxfpAEb7TxMM8GVPg19UEoCZSGJHnh4Vvg8uZ-eEs_Ci-vOIXqaaiffen7UN-HeiYfaB-U-aLyRaPaAIbSmfFRcullVV5IVVQNlx4eQzESBt7jHAytnIZz4IPTQjUjakf0ERAljSID5tWAwmYIUPvo--BU-uX7wcHRHh25tNKKqdKSbuA_tkHGYO_J_8pQlKFkofQmnvwYJxMKFthMaPaussZF2UcfJqcPs9PPfAb4rSEBH4dybA4T2Z_qUA50SQcQBu9PcuQJgQNo6G-Gcuhnxn5m6BfU74P-vYCEqBhwnm7GCo6zzYhX-QBTvM5HehZvx4ZVggeYr1bpSN8kW2jAaMpTceKyR_9ysawEqYeLSAIXHZyEC0cy5L84lFmQEQTwkkl72XM1HyWetfEUj-l0hPEbPRJ9GPI4SEhTjCbxyb_vGRI4AhsqnsiidfkSHkXgTyLyidelzQtuyCQhHfullwYBe59nHLfJocFtfCCAKtziQwk_fdLGB5fpYQd8nucwZHmuFdJDDyA5dMilfSM6B5Rn5YiqEYVWl-wFmOIB5RmgueHZJ8M3k-EvDRHinljynTeQ6o6ej8feqy_mU0FkjXqm3QMVjpfxMq65u1n92hPhEnpNr6JJQmlG0m2xpqssKXBerBOaV2lON2zlPtHMjPI3xpIbyyW1k37DrK5HzvUXA1ysuk8kTWdsq1WtmTFz6ZvLPtsgdDvcuSb3bL9IV43krbKwEvwHtCGk_Cq67H6xJMKc8KYVDN1F-AFy9wjv0Z_73W5S7_IL0g-4vpas6OrZq_N3pU4GCX7yz63w__x5sWBc1sh9ymcl4iY8UGsmSUMK93iZ9ZvGr5i7P57-G524EKxEnzncJRz05dQFQNbb95ZNz8xHhgyrK9IJi4jmhqGCUTgJkKqcVpUSQr2BNlS5DAu9HRncdvP4z-fHRZR-q5m9U02j5A8ueUNEeOVxz1AR3rxo6t587tC9sQ5to3Qf5THyN2iDCJKdEHDhHca2bghukFSo8VIRdc9aldIw9M_NDwwiiCxDNQObLr_Q0bZ1t3__fnHtkSzCu0FT8CRw_y2jYDRewTpzT2DzFxX_YZab558_Z3Im6B4Bho9WoPPXl8sf-z2M-GO_f3Qjf5-Pf4cmnf6LC_Gi4UxD8wHSQXj4dOHqo7duytu03KZbcsNuk3WW4DiPcXxzvCXbDK9YydZJtUriDalYnKTrdLXdlCwpi_yG3-IYr-I0XuEYx8lmmWRVmm3LVb6Kc7qheZTFrCFcLN26Vrq-cX94cJvg7RZvb9z3OeP-aANjyd6Qa4XltLq_0bduQyq62kRZLLixZhJjuRXs9mUI4Lcjk37R-DXBpdVcGk6Rm46bTovb3_8biaBtf4v_NwAA___IBnJ3">