<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/129516>129516</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            MachineCSE may not eliminate subexpression compeletely, result in more register using。
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            new issue
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          emelliu
      </td>
    </tr>
</table>

<pre>
    The case is complicate, after simplifying mir like this.
```
bb.0:
    def %a
    def %b

bb.1:
   successors: %bb.2, %bb.3
   ...
   %cmp = cmp  xxx
    branch  %bb.3, %cmp
    jmp %bb.2
bb.2:
    %1 = MUL_F32  %a, %b
    %2 = MUL_F32  %1, %c
    %3 = FSUB  %1, %2
    %4 = MAX  %3, %d
    ...
    jmp %bb.4
bb.3:
    %4 = MUL_F32  %a, %b
    %5 = MUL_F32  %4, %c
    %6 = FSUB  %4, %5
    %7 = FSUB %6, %c 
    ...

bb.4:
    ...
```
The expectation is machinecse can hoist common expression <%1,%2,%3> and <%4, %5,%6>
but the reality is that after running machine-cse two times,  it hoists <%1,%2> and <%4, %5> , so need more register to store temp value %4 and %5, if I run machine-cse once again, the %3 and %6 can be hoisted.

So I think machine cse has some problem。

I create new issue with new git account,  please close the https://github.com/llvm/llvm-project/issues/128862。

</pre>
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