<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/129401>129401</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            Improve `llvm.ucmp.i8.i1` codegen
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            new issue
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          scottmcm
      </td>
    </tr>
</table>

<pre>
    (Context: I was making a rustc PR and accidentally regressed `bool::cmp` by having it use `llvm.ucmp`, thus this bug that it would be nice if `ucmp` just was smart about it.)

`llvm.ucmp.i8.i1(a, b)` is actually the same as just `zext(a) - zext(b)`: <https://alive2.llvm.org/ce/z/oHq3bh>

But today they don't codegen the same: <https://llvm.godbolt.org/z/nxWdYhvTo>

```llvm
define noundef range(i8 -1, 2) i8 @src(i1 noundef zeroext %a, i1 noundef zeroext %b) unnamed_addr {
start:
  %0 = call i8 @llvm.ucmp.i8.i1(i1 %a, i1 %b)
  ret i8 %0
}

define noundef range(i8 -1, 2) i8 @tgt(i1 noundef zeroext %a, i1 noundef zeroext %b) unnamed_addr {
start:
  %aa = zext i1 %a to i8
  %bb = zext i1 %b to i8
  %0 = sub nsw i8 %aa, %bb
  ret i8 %0
}
```
on x64 gives
```asm
src:                                    # @src
        cmp dil, sil
        seta    al
        sbb     al, 0
        ret
tgt: # @tgt
        mov     eax, edi
        sub al, sil
        ret
```

I don't know if it's better to InstSimplify the `ucmp` to `sext(b) + zext(a)` or to improve the codegen for the `i1` case, but either way, it'd be nice if the intrinsic worked optimally for `i1` in addition to the wider widths.

</pre>
<img width="1" height="1" alt="" src="http://email.email.llvm.org/o/eJy0VU9v-zYM_TTKhWggy_njHHxw2wXrbdgGDDsNksXY-tWWMolO2n76gYqbplsHbIdfEMCwyff4SNHPOiXXecRarO_F-nGhJ-pDrFMbiMZ2XJhgX2uhqofgCV9IlA08wVknGPWz8x1oiFOiFn76GbS3oNvWWfSkh-EVInYRU0ILYiNNCIMoG1E27XgUGwnmFXp9Yg5HMCXkpGE4jcvpkiDUA1A_JaDeJTBTB9Rr4uRzmAYLBsG7FsEdGDmD4NuUKOtLo44E2oSJMUuhdkI2_L-psnTV0hVCVZqLGc7ZSHAJdEtTboF6hKRHBJ0u1GIj33gOGbODO5jvZjDPR5QPPdExcbdqL9ReD-6EapnLhtgJtW9RqP2bUPvw45-l6UX5w0Xc_URAwepc-BVs8EJtCdpgsUN_VfNllUzfBWvCQHMZruBffrO_96dfw7UIy8x_RgjZWDw4j-DD5C0eIGrfoVCVq-Cu4LkobtRVIFYyxZYjxTX5DWPAFwKh1nmGX4d4ODB5r0e0f2hrI4jtvZBNIh15pYRsgPMkiPIRWj0Mc71_npQrbmvN3BkfkTJKrSU3uX28dPs_uqOOvmd3Wuf2eGFm7RoogKveE4z5e4L5nHCZT5oM-HSem9VZWUb_-xjeT1zIJnh42aygcydMtyGdeBf4gMsG_sNPqPJ9I-QV0I5HsG5gRckNN4GEpPmqPz00BuaH6gHkTSQiCdnwefCmXyrx3UfGGE75ivqFwWjdLfFkZtLPKi60t9MQsnm6vmbPPpzZThwJtU1gkAgjn8CTT_SLG4-DO1ws4cZwKPBd-nABEOoebjyCk0KmceMxhhNmhvdX-sChC6MrOLXVCbMbTQToqMcIZ_2at49lffI9BjpP0fnkWjiH-IwWwpHcmM2Lua-8zoO21pELnrUw9OwssztLfVoK2SxsXdpdudMLrIvtSlYbta1Wi77ebI0u9Q6rXbU-7AweWr1pVbFS7XZbVdYsXK2kWstSFkqud6vVUuMON0apoqhUVZRarCSO2g1XE1y4lCasC7VbyWIxaINDyt8gpTyeIUeFUvxJijWD7szUJbYElyh90JCjAeunebJfmDuP9DLrxRSH-rNndo76ySzbMM4GOl_ujjF8w5aE2mclSaj9LPVUq78CAAD__wR6IjY">