<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/128650>128650</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            AMDGPU GlobalIsel mishandles readfirstlane lowering with 64-bit element vectors
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            backend:AMDGPU,
            llvm:globalisel,
            crash-on-valid
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
            vikramRH
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          arsenm
      </td>
    </tr>
</table>

<pre>
    d7903c9f28bdfd17fcc2d5be1096c504b6a94ec1 added commented out tests which fail with globalisel. The vector construction assumes 32-bit elements:

```
RUN: at line 3: /Users/matt/src/llvm-project/build_rel_with_debinfo/bin/llc -mtriple=amdgcn--amdhsa -mcpu=fiji -verify-machineinstrs -global-isel -global-isel-abort=2 < /Users/matt/src/llvm-project/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readfirstlane.ll | /Users/matt/src/llvm-project/build_rel_with_debinfo/bin/FileCheck -check-prefix=CHECK-GISEL -enable-var-scope /Users/matt/src/llvm-project/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readfirstlane.ll
+ /Users/matt/src/llvm-project/build_rel_with_debinfo/bin/llc -mtriple=amdgcn--amdhsa -mcpu=fiji -verify-machineinstrs -global-isel -global-isel-abort=2
+ /Users/matt/src/llvm-project/build_rel_with_debinfo/bin/FileCheck -check-prefix=CHECK-GISEL -enable-var-scope /Users/matt/src/llvm-project/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readfirstlane.ll

# After Legalizer
# Machine code for function test_readfirstlane_v2i64: IsSSA, TracksLiveness, Legalized
Function Live Ins: $sgpr4_sgpr5 in %2, $sgpr6_sgpr7 in %3, $sgpr8_sgpr9 in %4, $sgpr10_sgpr11 in %5, $sgpr12 in %6, $sgpr13 in %7, $sgpr14 in %8, $sgpr15 in %9

bb.1 (%ir-block.0):
 liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5
  %12:_(s32) = COPY $vgpr2
  %13:_(s32) = COPY $vgpr3
  %14:_(s32) = COPY $vgpr4
  %15:_(s32) = COPY $vgpr5
  %24:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), %12:_(s32)
  %25:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), %13:_(s32)
 %26:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), %14:_(s32)
  %27:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), %15:_(s32)
  %18:_(<2 x s64>) = G_BUILD_VECTOR %24:_(s32), %25:_(s32), %26:_(s32), %27:_(s32)
  %19:sgpr_128 = COPY %18:_(<2 x s64>)
  INLINEASM &"; use $0" [sideeffect] [attdialect], $0:[reguse:SGPR_128], %19:sgpr_128
  SI_RETURN

# End machine code for function test_readfirstlane_v2i64.

*** Bad machine code: G_BUILD_VECTOR result element type must match source type ***
- function: test_readfirstlane_v2i64
- basic block: %bb.1  (0x151098440)
- instruction: %18:_(<2 x s64>) = G_BUILD_VECTOR %24:_(s32), %25:_(s32), %26:_(s32), %27:_(s32)

*** Bad machine code: G_BUILD_VECTOR must have an operand for each elemement ***
- function:    test_readfirstlane_v2i64
- basic block: %bb.1  (0x151098440)
- instruction: %18:_(<2 x s64>) = G_BUILD_VECTOR %24:_(s32), %25:_(s32), %26:_(s32), %27:_(s32)
LLVM ERROR: Found 2 machine code errors.
PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the c
```
</pre>
<img width="1" height="1" alt="" src="http://email.email.llvm.org/o/eJzcV19v27oO_zTKC-HAlmwnechDmj9dcNO0SNoB9ymQJTrWKtuBJGfb_fQXctw07Wl3toPtYOcARiKTNP_8SBEkt1btK8QxSa4IpUf1aHi5-UAoJcmsxxtX1GbMjcWq7GW1_DqWg1HIxCinw0zmMhrkQlCZZBiFo1QkYZylfBSjiIBLiRJEXZZYOZRQNw4cWmfhc6FEATlXGj4rV8Be1xnXyqLuw32BcEThagOirqwzjXCqroBb25RogdEgUw5Qo1drCZuQsH3SsHvCyeZhTdgEuAOtKgTmXwhdPFg0ltBFyZ0jdGGNIHSh9bEMDqb-hMITs0ZpuTOod96zncRMVXntGapqpQUEpTPqoJGwGS_lXlRBwEtZWA5BKQ4NYbNcfVIQHNGo_GtQclGoCpWPxUJwijXwwb54CXhWG0fYjAJh0-91178SuvCwErqY1hKv0fs5uZld3z10Av2Tm32DXObKWKd5hX2tgQy-29Cf4LJQGqcFikcIhP8LDgZz9YWw2fTDfPqf4Hq5na8gwIpnGoMjN4EV9QH_ljB9cdCrf1AB_FSHf_fM-FgZTHKHBla451r9D01HvTkhB6KWCHltIG-qUzfw9nYv1O2OVKWxv-lLu91OCJ3CveHi0a7UESu01lOeDEgSThZPurwALCt76hKx3R9MvPO_CagKCE2o_7TjpC1n0HHYBWfYckYdJ77gRGHLiqKOl1zyaEdML4msIw4uiXFHHF4Sn3wcnbDMsn4EhA4JTZQJMl2Lx35I6OjUJkGro6_DLtLj_mDCTpk_RxdnenFmF-f44px4ld54RAmb7AgdWkYJHQFhM5je3v33WdmTIPu2IDsLxt8WjM-CybcFzz7SNzRe75br-81yvV1Od9Pb9cf55nq-vgdVOaMqq4QHMg7frWCPa4vGawDONt9w7ufZZH-w6U2mv9Jk_HaYg19pM3nTZjTsyIRNKXwB6-_-_Nn61cNyNdt9nE_vbzdvpL9T_ipBT9T0TergbUf83fJXcRfR4WX5ve9i--lyvVqu55PtDRCa-mmLXUFjfd-NQ0IpkOTKKomY577RJjNP4M5JxfWJ0F3E0F_t5MrgvrFI2GR7fbfxrpwlXnrY2t4ud5v5_cNm_dyA55WE8ofbbf9JQffAFX-pxneaV8kwaBt9HuDAfT0glI11UHInCrB1YwSeyGe9JJwEZ2-8znf7vxfMuFUC2uZ36nRJ2xZ9Xwy_REkUjoZxHJ4SEYB6HjI76d-htn4U1RbBgh8ReAX1AQ2vZJtD5KI4gd3C_T6kAP9-VFerjzcw32xuN96pRd1UEujLukdjamN9Yd-t5pPtHGyTlcoBh6zZg8FDbRy4GgrnDu32QReELvbKFU3WF3X5PBO9mpSUtQ36cQp8alQldCMRXIEgLteXnhwzOWIj3sNxNIjDOB2lw7RXjNNUxFSwmFE6yJHyhCdMpjkNaRyG2TDpqTENaRJSmoSDeBimfTrK4xhpNmRZOEowI3GIJVe637bd2ux7rU_jiA7TJOxpnqG23R6YcfGIlSRs8jTJ-YmAUNoGxybPK9uZIwy3RVBXwZFrJbsF0oxbGLJmb32_V9bZZ_NOOY3jkwG4bjUu_VhcKlvwSmq08KIaQdef0ahqf1ob0_hyFey2RttrjB7_9ex0YBzH9P8BAAD__xubhaM">