<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/126781>126781</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            [AMDGPU] getSubRegs in SIRegisterInfo.td can be simplified
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          jurahul
      </td>
    </tr>
</table>

<pre>
    It seems the code is essentially slicing a large list using conditions, can be simplified to an assert (for size check) and a list slice, using the `ret32` list and size. 

Simple starter task for someone interested in TD files. Verify that the generated GenRegInfo file is the same before/after the fix.
</pre>
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